公开(公告)号：US20100118636A1

公开(公告)日：2010-05-13

申请号：US12688254

申请日：2010-01-15

申请人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Lynne M. Gignac ,  Wai-Kin Li ,  Ping-Chuan Wang

IPC分类号： G11C17/16 ,  H01L23/525 ,  H01L21/44

CPC分类号： G11C17/16 ,  H01L21/7682 ,  H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： An electrically reprogrammable fuse comprising an interconnect disposed in a dielectric material, a sensing wire disposed at a first end of the interconnect, a first programming wire disposed at a second end of the interconnect, and a second programming wire disposed at a second end of the interconnect, wherein the fuse is operative to form a surface void at the interface between the interconnect and the sensing wire when a first directional electron current is applied from the first programming wire through the interconnect to the second programming wire, and wherein, the fuse is further operative to heal the surface void between the interconnect and the sensing wire when a second directional electron current is applied from the second programming wire through the interconnect to the first programming wire.

摘要翻译： 一种电可重新编程的保险丝，其包括设置在电介质材料中的互连，布置在所述互连的第一端的感测线，布置在所述互连的第二端的第一编程线，以及设置在所述互连的第二端的第二编程线 其中当从所述第一编程线通过所述互连件施加第一定向电子线到所述第二编程线时，所述保险丝可操作以在所述互连和感测线之间的界面处形成表面空隙，并且其中，所述保险丝是 当从所述第二编程线通过所述互连件施加第二编程线到所述第一编程线时，还可操作以治愈所述互连和所述感测线之间的表面空隙。

公开(公告)号：US07692439B2

公开(公告)日：2010-04-06

申请号：US12154304

申请日：2008-05-22

申请人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Birendra Agarwala ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Ronald G. Filippi ,  Jason P. Gill ,  Tom C. Lee ,  Baozhen Li ,  Paul S. McLaughlin ,  Du B. Nguyen ,  Hazara S. Rathore ,  Timothy D. Sullivan ,  Chih-Chao Yang

IPC分类号： G01R31/02 ,  H01L23/58 ,  G01N25/20

CPC分类号： G01R31/2858 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure representative of a conductive interconnect of a microelectronic element is provided, which may include a conductive metallic plate having an upper surface, a lower surface, and a plurality of peripheral edges extending between the upper and lower surfaces, the upper surface defining a horizontally extending plane. The structure may also include a lower via having a top end in conductive communication with the metallic plate and a bottom end vertically displaced from the top end. A lower conductive or semiconductive element can be in contact with the bottom end of the lower via. An upper metallic via can lie in at least substantial vertical alignment with the lower conductive via, the upper metallic via having a bottom end in conductive communication with the metallic plate and a top end vertically displaced from the bottom end. The upper metallic via may have a width at least about ten times than the length of the metallic plate and about ten times smaller than the width of the metallic plate. The structure may further include an upper metallic line element in contact with the top end of the upper metallic via.

摘要翻译： 提供了表示微电子元件的导电互连的结构，其可以包括具有上表面，下表面和在上表面和下表面之间延伸的多个周边边缘的导电金属板，上表面限定水平 延伸平面 该结构还可以包括具有与金属板导电连通的顶端和从顶端垂直移位的底端的下通孔。 下导电或半导体元件可以与下通孔的底端接触。 上金属通孔可以与下导电通孔至少基本垂直对准，上金属通孔具有与金属板导电连通的底端和从底端垂直移位的顶端。 上部金属通孔的宽度可以比金属板的长度至少大约十倍，并且比金属板的宽度小约十倍。 该结构还可以包括与上金属通孔的顶端接触的上金属线元件。

公开(公告)号：US20090297759A1

公开(公告)日：2009-12-03

申请号：US12127878

申请日：2008-05-28

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Charles C. Goldsmith ,  Ping-Chuan Wang ,  Chih-Chao Yang

IPC分类号： B05D5/12 ,  B32B3/02

CPC分类号： H01L21/76877 ,  H01L21/76883

摘要： Recrystallization and grain growth of metal, such as Cu, is achieved at higher anneal temperatures of 150° C. to 400° C., for example, for short anneal times of five to sixty minutes by forming a metal stress locking layer on the Cu before anneal and chemical-mechanical polishing. The stress locking layer extends the elastic region of the Cu by suppressing atom diffusion to the free surface, resulting in near zero tensile stress at room temperature after anneal. Stress voiding, which creates reliability problems, is thereby avoided. Improved grain size and texture are also achieved. The stress locking layer is removed after anneal by chemical-mechanical polishing leaving the Cu interconnect with low stress and improved grain size and texture.

摘要翻译： 在150℃至400℃的较高退火温度下实现诸如Cu的金属的重结晶和晶粒生长，例如，通过在Cu上形成金属应力锁定层，例如在短至五至六十分钟的短退火时间 在退火和化学机械抛光之前。 应力锁定层通过将原子扩散抑制到自由表面而延伸Cu的弹性区域，导致退火后在室温下拉伸应力接近零。 从而避免了造成可靠性问题的应力消除。 也实现了改善的晶粒尺寸和纹理。 通过化学机械抛光退火后去除应力锁定层，使Cu互连具有低应力和改善的晶粒尺寸和纹理。

公开(公告)号：US07585764B2

公开(公告)日：2009-09-08

申请号：US11161599

申请日：2005-08-09

申请人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Lawrence A. Clevenger ,  Andrew P. Cowley ,  Jason P. Gill ,  Baozhen Li ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L21/76865 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76886

摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

摘要翻译： 制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。 该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。 该方法产生防止开路的结构。

公开(公告)号：US20090108855A1

公开(公告)日：2009-04-30

申请号：US12348434

申请日：2009-01-05

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang

IPC分类号： G01R27/08

CPC分类号： G01R31/2858

摘要： A test structure for electromigration and related method are disclosed. The test structure may include an array of a plurality of multilink test sets, each multilink test set including a plurality of metal lines positioned within a dielectric material and connected in a serial configuration; each multilink test set being connected in a parallel configuration with the other multilink test sets, the parallel configuration including a first electrical connection to a cathode end of a first metal line in each multilink test set and a second electrical connection to an anode end of a last metal line in each multilink test set.

摘要翻译： 公开了用于电迁移的测试结构及相关方法。 测试结构可以包括多个多链测试集的阵列，每个多链测试集包括定位在电介质材料内并以串联配置连接的多个金属线; 每个多链路测试集合以与其他多链路测试集合的并行配置连接，所述并行配置包括到每个多链路测试集合中的第一金属线的阴极端的第一电连接和到第一金属线的阳极端的第二电连接 每条多链测试集中的最后一条金属线。

公开(公告)号：US20090033351A1

公开(公告)日：2009-02-05

申请号：US11830368

申请日：2007-07-30

申请人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang

发明人： Kaushik Chanda ,  Ronald G. Filippi ,  Ping-Chuan Wang

IPC分类号： G01R31/26

CPC分类号： G01R31/2858

摘要： A test structure for electromigration and related method are disclosed. The test structure may include an array of a plurality of multilink test sets, each multilink test set including a plurality of metal lines positioned within a dielectric material and connected in a serial configuration; each multilink test set being connected in a parallel configuration with the other multilink test sets, the parallel configuration including a first electrical connection to a cathode end of a first metal line in each multilink test set and a second electrical connection to an anode end of a last metal line in each multilink test set.

公开(公告)号：US20080197500A1

公开(公告)日：2008-08-21

申请号：US11675705

申请日：2007-02-16

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Ping-Chuan Wang

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Ping-Chuan Wang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76883 ,  H01L21/76885 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

摘要： A structure and method of fabricating an interconnect structures with bi-layer metal cap is provided. In one embodiment, the method includes forming an interconnect feature in a dielectric material layer; and forming a bi-layer metallic cap on a top surface of the interconnect feature. The method further includes depositing a blanket layer of a dielectric capping layer, wherein the depositing covers an exposed surface of the dielectric material layer and a surface of the bi-layer metallic cap. The bi-layer metallic cap includes a metal capping layer formed on a conductive surface of the interconnect feature; and a metal nitride formed on a top portion of the metal capping layer. An interconnect structure is also described having an interconnect feature formed in a dielectric layer; a bi-layer metallic cap formed on a top portion of the interconnect feature; and a dielectric capping layer formed over the bi-layer metallic cap.

摘要翻译： 提供了制造具有双层金属盖的互连结构的结构和方法。 在一个实施例中，该方法包括在电介质材料层中形成互连特征; 以及在所述互连特征的顶表面上形成双层金属帽。 该方法还包括沉积介电覆盖层的覆盖层，其中沉积覆盖电介质材料层的暴露表面和双层金属帽的表面。 双层金属盖包括形成在互连特征的导电表面上的金属覆盖层; 以及形成在金属覆盖层的顶部上的金属氮化物。 还描述了具有形成在电介质层中的互连特征的互连结构; 形成在互连特征的顶部上的双层金属帽; 以及形成在双层金属盖上的电介质覆盖层。

公开(公告)号：US07287325B2

公开(公告)日：2007-10-30

申请号：US10908392

申请日：2005-05-10

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01K3/10

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US20070063348A1

公开(公告)日：2007-03-22

申请号：US11162666

申请日：2005-09-19

申请人： Chih-Chao Yang ,  Kaushik Chanda ,  Lawrence Clevenger ,  Yun-Yu Wang ,  Daewon Yang

发明人： Chih-Chao Yang ,  Kaushik Chanda ,  Lawrence Clevenger ,  Yun-Yu Wang ,  Daewon Yang

IPC分类号： H01L23/52 ,  H01L21/4763

CPC分类号： H01L21/76834 ,  H01L21/76832 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of making the same are provided. The interconnect structure includes a dielectric layer having a patterned opening, a metal feature disposed in the patterned opening, and a dielectric cap overlying the metal feature. The dielectric cap has an internal tensile stress, the stress helping to avoid electromigration from occurring in a direction away from the metal line, especially when the metal line has tensile stress.

摘要翻译： 提供了互连结构及其制造方法。 互连结构包括具有图案化开口的电介质层，设置在图案化开口中的金属特征以及覆盖金属特征的电介质盖。 电介质盖具有内部拉伸应力，该应力有助于避免在远离金属线的方向上发生电迁移，特别是当金属线具有拉伸应力时。

公开(公告)号：US20070037403A1

公开(公告)日：2007-02-15

申请号：US11161599

申请日：2005-08-09

申请人： Kaushik Chanda ,  Lawrence Clevenger ,  Andrew Cowley ,  Jason Gill ,  Baozhen Li ,  Chih-Chao Yang

发明人： Kaushik Chanda ,  Lawrence Clevenger ,  Andrew Cowley ,  Jason Gill ,  Baozhen Li ,  Chih-Chao Yang

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/76865 ,  H01L21/76805 ,  H01L21/76846 ,  H01L21/76886

摘要： A method of fabricating a device includes depositing a electromigration (EM) resistive material in an etched trench formed in a substrate and a wiring layer. The EM resistive material is formed in electrical contact with an underlying diffusion barrier layer and wiring layer. The method further includes forming a via structure in electrical contact with the EM resistive material and the wiring layer. The method results in a structure which prevents an open circuit.

摘要翻译： 制造器件的方法包括在形成在衬底和布线层中的蚀刻沟槽中沉积电迁移（EM）电阻材料。 EM电阻材料形成为与下面的扩散阻挡层和布线层电接触。 该方法还包括形成与EM电阻材料和布线层电接触的通孔结构。 该方法产生防止开路的结构。