公开(公告)号：US20120267689A1

公开(公告)日：2012-10-25

申请号：US13089652

申请日：2011-04-19

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Kuang Yeu Hsieh

IPC分类号： H01L27/10 ,  H01L21/82

CPC分类号： H01L27/0688 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11578

摘要： An integrated circuit memory device, including a memory circuit and a peripheral circuit, is described which is suitable for low cost manufacturing. The memory circuit and peripheral circuit for the device are implemented in different layers of a stacked structure. The memory circuit layer and the peripheral circuit layer include complementary interconnect surfaces, which upon mating together establish the electrical interconnection between the memory circuit and the peripheral circuit. The memory circuit layer and the peripheral circuit layer can be formed separately using different processes on different substrates in different fabrication lines. This enables the use of independent fabrication process technologies, one arranged for the memory array, and another arranged for the supporting peripheral circuit. The separate circuitry can then be stacked and bonded together.

摘要翻译： 描述了包括存储器电路和外围电路的集成电路存储器件，其适用于低成本制造。 用于器件的存储器电路和外围电路被实现在堆叠结构的不同层中。 存储器电路层和外围电路层包括互补的互连表面，其在配合时一起建立存储器电路和外围电路之间的电互连。 存储电路层和外围电路层可以在不同的制造线路中的不同基板上使用不同的工艺分别形成。 这使得能够使用独立的制造工艺技术，一种被布置用于存储器阵列，另一种被布置用于支持外围电路。 然后可以将单独的电路堆叠并结合在一起。

公开(公告)号：US20120182808A1

公开(公告)日：2012-07-19

申请号：US13009464

申请日：2011-01-19

申请人： Hang-Ting Lue ,  Shih-Hung Chen

发明人： Hang-Ting Lue ,  Shih-Hung Chen

IPC分类号： G11C16/04 ,  H01L29/792 ,  H01L21/336

CPC分类号： H01L29/7926 ,  G11C16/0466 ,  G11C16/3418 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833

摘要： A memory device, a manufacturing method and an operating method of the same are provided. The memory device includes a substrate, stacked structures, a channel element, a dielectric element, a source element, and a bit line. The stacked structures are disposed on the substrate. Each of the stacked structures includes a string selection line, a word line, a ground selection line and an insulating line. The string selection line, the word line and the ground selection line are separated from each other by the insulating line. The channel element is disposed between the stacked structures. The dielectric element is disposed between the channel element and the stacked structure. The source element is disposed between the upper surface of the substrate and the lower surface of the channel element. The bit line is disposed on the upper surface of the channel element.

摘要翻译： 提供了一种存储器件，其制造方法和操作方法。 存储器件包括衬底，堆叠结构，沟道元件，电介质元件，源元件和位线。 堆叠结构设置在基板上。 每个堆叠结构包括串选择线，字线，接地选择线和绝缘线。 串选择线，字线和接地选择线通过绝缘线彼此分离。 通道元件设置在堆叠结构之间。 电介质元件设置在通道元件和堆叠结构之间。 源元件设置在基板的上表面和通道元件的下表面之间。 位线设置在通道元件的上表面上。

公开(公告)号：US20120182802A1

公开(公告)日：2012-07-19

申请号：US13239760

申请日：2011-09-22

申请人： Chun-Hsiung Hung ,  Hang-Ting Lue ,  Shih-Hung Chen

发明人： Chun-Hsiung Hung ,  Hang-Ting Lue ,  Shih-Hung Chen

IPC分类号： G11C16/04

CPC分类号： G11C5/06 ,  G11C7/18 ,  G11C13/0002 ,  G11C16/0483 ,  G11C17/16 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/10 ,  H01L27/1021 ,  H01L27/11206 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11578 ,  H01L29/792

摘要： A 3D integrated circuit memory array has a plurality of plane positions. Multiple bit line structures have a multiple sequences of multiple plane positions. Each sequence characterizes an order in which a bit line structure couples the plane positions to bit lines. Each bit line is coupled to at least two different plane positions to access memory cells at two or more different plane positions.

摘要翻译： 3D集成电路存储器阵列具有多个平面位置。 多个位线结构具有多个平面位置的多个序列。 每个序列表征位线结构将平面位置耦合到位线的顺序。 每个位线耦合到至少两个不同的平面位置以访问两个或更多个不同平面位置处的存储器单元。

公开(公告)号：US20120181701A1

公开(公告)日：2012-07-19

申请号：US13114931

申请日：2011-05-24

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Hong-Ji Lee ,  Chin-Cheng Yang

IPC分类号： H01L21/283 ,  H01L23/48

CPC分类号： H01L23/50 ,  H01L21/76805 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/76838 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5226 ,  H01L24/19 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/11206 ,  H01L27/11286 ,  H01L27/11565 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/00

摘要： A method provides electrical connections to a stack of contact levels of an interconnect region for a 3-D stacked IC device. Each contact level comprises conductive and insulation layers. A portion of any upper layer is removed to expose a first contact level and create contact openings for each contact level. A set of N masks is used to etch the contact openings up to and including 2N contact levels. Each mask is used to etch effectively half of the contact openings. When N is 3, a first mask etches one contact level, a second mask etches two contact levels, and a third mask etches four contact levels. A dielectric layer may be formed on the sidewalls of the contact openings. Electrical conductors may be formed through the contact openings with the dielectric layers electrically insulating the electrical conductors from the sidewalls.

摘要翻译： 一种方法提供了用于3-D堆叠IC器件的互连区域的接触电平堆叠的电连接。 每个接触层包括导电层和绝缘层。 去除任何上层的一部分以露出第一接触层并为每个接触层产生接触开口。 使用一组N个掩模来蚀刻直到并包括2N个接触电平的接触开口。 每个掩模用于有效地蚀刻半个接触开口。 当N为3时，第一掩模蚀刻一个接触电平，第二掩模蚀刻两个接触电平，并且第三掩模蚀刻四个接触电平。 电介质层可以形成在接触开口的侧壁上。 电导体可以通过接触开口形成，其中电介质层将电导体与侧壁电绝缘。

公开(公告)号：US20120181699A1

公开(公告)日：2012-07-19

申请号：US13024546

申请日：2011-02-10

申请人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yi-Hsuan Hsiao

发明人： Shih-Hung Chen ,  Hang-Ting Lue ,  Yi-Hsuan Hsiao

IPC分类号： H01L23/528 ,  H01L21/768

CPC分类号： H01L27/11582 ,  H01L27/11578

摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a first stacked structure, a second stacked structure, a dielectric element, and a conductive line. The first stacked structure and the second stacked structure are disposed on the substrate. Each of the first stacked structure and the second stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is disposed on the first stacked structure and the second stacked structure and includes a second dielectric portion. The first stacked structure and the second stacked structure are separated from each other by only the second dielectric portion. The conductive line is disposed on the stack sidewalls of the first stacked structure and the second stacked structure far from the second dielectric portion.

摘要翻译： 提供了一种半导体结构及其制造方法。 半导体结构包括基板，第一堆叠结构，第二堆叠结构，电介质元件和导线。 第一堆叠结构和第二堆叠结构设置在基板上。 第一堆叠结构和第二堆叠结构中的每一个包括交替堆叠的导电条和绝缘条。 导电条通过绝缘条彼此分离。 电介质元件设置在第一堆叠结构和第二堆叠结构上并且包括第二电介质部分。 第一堆叠结构和第二堆叠结构仅通过第二电介质部分彼此分离。 导电线设置在第一堆叠结构的堆叠侧壁和远离第二电介质部分的第二堆叠结构中。

公开(公告)号：US20120181580A1

公开(公告)日：2012-07-19

申请号：US13008410

申请日：2011-01-18

申请人： Hang-Ting Lue ,  Shih-Hung Chen

发明人： Hang-Ting Lue ,  Shih-Hung Chen

IPC分类号： H01L27/08 ,  H01L21/822

CPC分类号： H01L27/0688 ,  H01L21/8221 ,  H01L21/823487 ,  H01L27/11578 ,  H01L29/792

摘要： A semiconductor structure and a manufacturing method of the same are provided. The semiconductor structure includes a substrate, a stacked structure, a dielectric element, a conductive line, and conductive islands. The stacked structure is formed on the substrate. The stacked structure includes conductive strips and insulating strips stacked alternately. The conductive strips are separated from each other by the insulating strips. The dielectric element is formed on the stacked structure. The conductive line is formed on the dielectric element. The conductive line is extended in a direction perpendicular to a direction which the stacked structure is extended in. The conductive islands are formed on the dielectric element. The conductive islands on the opposite sidewalls of the single stacked structure are separated from each other.

摘要翻译： 提供了一种半导体结构及其制造方法。 半导体结构包括衬底，层叠结构，电介质元件，导电线和导电岛。 层叠结构形成在基板上。 堆叠结构包括交替堆叠的导电条和绝缘条。 导电条通过绝缘条彼此分离。 电介质元件形成在堆叠结构上。 导电线形成在电介质元件上。 导电线在垂直于层叠结构延伸的方向的方向上延伸。导电岛形成在电介质元件上。 单个堆叠结构的相对侧壁上的导电岛彼此分离。

公开(公告)号：US20120104542A1

公开(公告)日：2012-05-03

申请号：US13014048

申请日：2011-01-26

申请人： Shih-Hung Chen

发明人： Shih-Hung Chen

IPC分类号： H01L23/58 ,  H01L21/76

CPC分类号： H01L29/417 ,  H01L21/743 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/1022 ,  H01L29/41708

摘要： The invention relates to a semiconductor structure and a manufacturing method of the same. The semiconductor structure includes a semiconductor substrate, an isolation layer, a first metal layer, and a second metal layer. The semiconductor substrate includes an upper substrate surface and a semiconductor device below the upper substrate surface. The isolation layer has opposite a first side wall and a second side wall. The first metal layer is disposed on the upper substrate surface. The first metal layer and the second metal layer are disposed on the first side wall and the second side wall, respectively. A lower surface of the second metal layer is below the upper substrate surface.

摘要翻译： 本发明涉及一种半导体结构及其制造方法。 半导体结构包括半导体衬底，隔离层，第一金属层和第二金属层。 半导体衬底包括上衬底表面和在上衬底表面下方的半导体器件。 隔离层与第一侧壁和第二侧壁相对。 第一金属层设置在上基板表面上。 第一金属层和第二金属层分别设置在第一侧壁和第二侧壁上。 第二金属层的下表面在上基板表面下方。

公开(公告)号：US08158965B2

公开(公告)日：2012-04-17

申请号：US12026342

申请日：2008-02-05

申请人： Shih-Hung Chen

发明人： Shih-Hung Chen

IPC分类号： H01L47/00

CPC分类号： H01L45/1233 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/008 ,  G11C2213/79 ,  H01L45/06 ,  H01L45/1286 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1666

摘要： Memory devices are described along with manufacturing methods. A memory device as described herein includes a bottom electrode and a first phase change layer comprising a first phase change material on the bottom electrode. A resistive heater comprising a heater material is on the first phase change material. A second phase change layer comprising a second phase change material is on the resistive heater, and a top electrode is on the second phase change layer. The heater material has a resistivity greater than the most highly resistive states of the first and second phase change materials.

摘要翻译： 存储器件与制造方法一起被描述。 如本文所述的存储器件包括底部电极和在底部电极上包括第一相变材料的第一相变层。 包括加热器材料的电阻加热器位于第一相变材料上。 包括第二相变材料的第二相变层位于电阻加热器上，顶电极位于第二相变层上。 加热器材料的电阻率大于第一和第二相变材料的最高电阻状态。

公开(公告)号：US20110304010A1

公开(公告)日：2011-12-15

申请号：US12851539

申请日：2010-08-05

申请人： Zhe-Wei Jiang ,  Ding-Ming Kwai ,  Shih-Hung Chen

发明人： Zhe-Wei Jiang ,  Ding-Ming Kwai ,  Shih-Hung Chen

IPC分类号： H01L23/60

CPC分类号： H01L25/0657 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/60 ,  H01L24/05 ,  H01L24/16 ,  H01L24/94 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01014 ,  H01L2924/01046 ,  H01L2924/14 ,  H01L2224/05552

摘要： An electrostatic discharge (ESD) protection scheme for a semiconductor device stacking process is provided, in which an equivalent electrical resistance of a specific path is designed to be less than an equivalent electrical resistance of other paths. Accordingly, when a first active layer and a second active layer in the semiconductor device are stacked, by designing suitable ESD protection cells on such a specific path, electrical charges accumulated on the top layer wafer (or die) select such a specific path over the other paths to be released to the grounded bottom layer wafer (or die), so as to achieve an ESD protection effect. In addition, since such a specific path also serves as a heat dissipation path in a three dimensional integrated circuit (3D IC), an overall heat resistance of the 3D IC may be reduced to improve a heat dissipation effect.

摘要翻译： 提供了一种用于半导体器件堆叠处理的静电放电（ESD）保护方案，其中特定路径的等效电阻被设计为小于其他路径的等效电阻。 因此，当半导体器件中的第一有源层和第二有源层被堆叠时，通过在这样的特定路径上设计合适的ESD保护单元，积聚在顶层晶片（或管芯）上的电荷选择这样的特定路径 其他路径被释放到接地的底层晶片（或裸片）上，以达到ESD保护效果。 此外，由于这样的特定路径也用作三维集成电路（3D IC）中的散热路径，所以可以降低3D IC的整体耐热性，从而提高散热效果。

公开(公告)号：US20110013326A1

公开(公告)日：2011-01-20

申请号：US12891474

申请日：2010-09-27

申请人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

发明人： Ming-Dou Ker ,  Shih-Hung Chen ,  Kun-Hsien Lin

IPC分类号： H02H9/04 ,  H01L27/06

CPC分类号： H01L23/62 ,  H01L27/0262 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device for electrostatic discharge (ESD) protection comprises a silicon controlled rectifier (SCR) including a semiconductor substrate, a first well formed in the substrate, a second well formed in the substrate, a first p-type region formed in the first well to serve as an anode, and a first n-type region partially formed in the second well to serve as a cathode, a p-type metal-oxide-semiconductor (PMOS) transistor formed in the first well including a gate, a first diffused region and a second diffused region separated apart from the first diffused region, a second n-type region formed in the first well electrically connected to the first diffused region of the PMOS transistor, and a second p-type region formed in the substrate electrically connected to the second diffused region of the PMOS transistor.

摘要翻译： 一种用于静电放电（ESD）保护的半导体器件包括可控硅整流器（SCR），其包括半导体衬底，形成在衬底中的第一阱，在衬底中形成的第二阱，形成在第一阱中的第一p型区 用作阳极，以及部分地形成在第二阱中用作阴极的第一n型区域，形成在包括栅极的第一阱中的p型金属氧化物半导体（PMOS）晶体管，第一扩散层 区域和与第一扩散区域分离的第二扩散区域，形成在电连接到PMOS晶体管的第一扩散区域的第一阱中的第二n型区域和形成在衬底中的第二p型区域电连接 到PMOS晶体管的第二扩散区域。