摘要:
A semiconductor die having raised conductive bumps on its surface for connecting to other devices or systems is disposed on a face of a preformed planar structure (interposer) having through holes. Solder joints with conductive bumps on an underlying substrate are formed in the through holes. In one embodiment, the interposer is dissolvable. In another embodiment, the through holes are at least partially filled with a conductive material for electrically connecting to the die. In another embodiment, the through holes are angled so that the interposer acts as a pitch spreader or adapter. In another embodiment, ball bumps are disposed on a side of the interposer away from the die. Various other embodiments are directed to multi-tier flip-chip arrays employing preformed planar structures between tiers.
摘要:
A polysilicon interconnect is formed on a microelectronic circuit substrate for conducting signals from a driver to a non-polycrystalline silicon contact which has higher impedance than the interconnect. A plurality of electronic "speed bumps" are spaced along the interconnect for disturbing or disrupting signals propagating along the interconnect toward the contact and thereby reducing undesirable back reflection and ringing. The speed bumps can include capacitance altering elements in the form of dielectric strips, or resistance altering elements in the form of low resistance doped areas or high resistance amorphous areas. The speed bumps can include first and second elements having different values of capacitance or resistance which are spaced along the interconnect in alternating relation.
摘要:
Plastic (or resinous) materials used to package (or support) electronic devices typically have thermal coefficients of expansion exceeding that of the device to be packaged. A "loading" material (agent) having a coefficient of expansion significantly less than the "base" plastic material (molding compound), less than that of the die, and preferably zero or negative over a temperature range of interest, is mixed with the "base" plastic material to produce a plastic molding compound with a lower overall thermal coefficient of expansion. Titanium dioxide, zirconium oxide and silicon are discussed as loading agents. The loading material is mixed into the plastic molding compound in sufficient quantity to ensure that the resulting mixture exhibits an overall thermal coefficient of expansion that is more closely matched to that of the electronic device. Reduction of the absolute thermal coefficient of expansion of the plastic material (independent of any matching criteria) additionally serves to reduce thermal stress cracking of plastic package bodies during rapid thermal cycling, such as occurs during vapor soldering.
摘要:
Via filling is enhanced by the techniques of 1) providing pillars immediately underneath semiconductor features, such as metal layer contacts (inter-connection points), and 2) polishing off excess via-filling material so that the via-filling plug is flush with the topmost insulating layer. The pillars are provided under every feature over which a via will be formed, so that an insulating layer surrounding the via will be thinner at the location of the feature. If necessary, polishing is continued to thin the insulating layer so that the plugs in initially selectively under-filled vias are made flush with the insulating layer. Method and apparatus are disclosed.
摘要:
Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A stream of such radiation is concentrated and collimated by a concentrator, the output of which is disposed in close proximity to the sensitized surface of the wafer. In this manner, the sensitized surface can be converted from one chemical state to another chemical state, essentially point-by-point. By moving one or the other of the beam or the wafer, line features can be converted in the sensitized surface. Typically, non-converted areas of the sensitized surface are removed, for further processing a layer underlying the sensitized surface. The concentrator is useful in for directing a stream of radiation from a continuously emitting source, such as from a pellet of Cobalt-60, onto the sensitized surface of the wafer when a shutter mechanism is incorporated either upstream (towards the source) or downstream (towards the wafer) from the concentrator.
摘要:
A low dielectric insulation layer for an integrated circuit structure material, and a method of making same, are disclosed. The low dielectric constant insulation layer comprises a porous insulation layer, preferably sandwiched between non-porous upper and lower insulation layers. The presence of some gases such as air or an inert gas, or a vacuum, in the porous insulation material reduces the overall dielectric constant of the insulation material, thereby effectively reducing the capacitance of the structure. The porous insulation layer is formed by a chemical vapor deposition of a mixture of the insulation material and a second extractable material; and then subsequently selectively removing the second extractable material, thereby leaving behind a porous matrix of the insulation material, comprising the low dielectric constant insulation layer.
摘要:
A process for interconnecting conductive substrates using an interposer having conductive plastic filled vias. The process comprises the steps of forcing conductive plastic material through an end of the through holes in the interposer so that raised globs of the conductive plastic extend from an opposite end of the through holes. Then conductive pads of a first substrate are aligned and pressed against the raised globs such that the conductive plastic protrudes as bumps from the forcing ends of the through holes. Finally, conductive pads of a second substrate are aligned and pressed against the bumps.
摘要:
An apparatus and method for mounting and connecting a plurality of integrated circuit chip dice to a printed circuit substrate by means of a small circuit board (such as a Mini-Board) that may be adapted to attach and connect into a plurality of different types of printed circuit board systems. A pattern of conductors that monotonically increases in pitch and width from a central point on a planar structure to the perimeter edge of the structure allows matching of any type of printed circuit board connections. A standard Mini-Board may be fabricated and tested before attaching to an electronic system printed circuit board. Repair and rework is easily facilitated with a minimum amount of damage to a printed circuit board by utilizing the present invention. A plurality of active and passive electronic components may also be attached and connected to the planar structure of the present invention. A hybrid mini-system may be fabricated and tested before connecting it into a system printed circuit board.
摘要:
A preformed planar structure is interposed between the chip(s) and the substrate in a flip-chip structure, and establishes a minimum gap between the chip(s) and the substrate. Liquid flux may be applied to the preformed planar structure in order that flux is selectively applied to the solder balls (pads) on the chip and the substrate. The preformed planar structure may be provided with through holes in registration with the solder balls on the chip(s) and the substrate. In this case, liquid flux selectively fills the through holes for delivery to the solder balls during soldering. The through holes also aid in maintaining registration of the chip(s) and the substrate. The through holes may be sized to establish a predetermined mechanical structure of solder joints formed by the solder balls when fused together. The preformed planar structure has a planar core and opposing planar faces. The core is formed of thermosetting organic resin, such as polyimide, or non-organic material such as alumina, polished sapphire, beryllium oxide, aluminum nitride or anodized aluminum. The planar faces of the preformed planar structure are formed of thermoplastic resin or thermosetting material, such as polyacetal, epoxide resin or polystyrene. The preformed planar structure tends to draw the chip(s) together to the substrate, establishing a flip-chip structure of mechanical integrity. The preformed planar structure has a thickness of 5-50 microns, preferably on the order of 20-30 microns.
摘要:
Improved thermal and/or electrostatic discharge characteristics are realized in cavity-type semiconductor device assemblies by filling the cavity with either a thermally conductive fluid and/or an arc suppressing gas, or combinations thereof. The interior of the cavity, including the die, leads extending into the cavity, and connections between the die and the leads may be coated to provide protection from corrosive and/or electrical characteristics of the cavity-filling fluid (liquid or gas). The fluid may be introduced through a hole in a lid sealing the cavity, and the cavity is filled sufficiently that the fluid is in contact with the die at various spatial orientations of the package. A thermally-conductive fluid substantially filling the cavity provides improved thermal conduction from the die to the package body without the mechanical stress problems (e.g., thermally induced cracking) ordinarily associated with bonding solid materials to the die. An arc-suppressing gas filling the cavity provides significant suppression of electrical discharges, thereby producing a packaged semiconductor device with improved electrostatic characteristics.