CAPACITIVE MONITORS FOR DETECTING METAL EXTRUSION DURING ELECTROMIGRATION
    82.
    发明申请
    CAPACITIVE MONITORS FOR DETECTING METAL EXTRUSION DURING ELECTROMIGRATION 失效
    用于检测电解过程中金属挤压的电容监测器

    公开(公告)号:US20060066314A1

    公开(公告)日:2006-03-30

    申请号:US10711641

    申请日:2004-09-29

    IPC分类号: G01R31/08

    摘要: A method and apparatus for detecting metal extrusion associated with electromigration (EM) under high current density situations within an EM test line by measuring changes in capacitance associated with metal extrusion that occurs in the vicinity of the charge carrying surfaces of one or more capacitors situated in locations of close physical proximity to anticipated sites of metal extrusion on an EM test line are provided. The capacitance of each of the one or more capacitors is measured prior to and then during or after operation of the EM test line so as to detect capacitance changes indicating metal extrusion.

    摘要翻译: 一种用于在EM测试线中的高电流密度情况下检测与电迁移(EM)有关的金属挤出的方法和装置,其通过测量在位于一个或多个电容器中的一个或多个电容器的电荷承载表面附近的与金属挤出相关的电容的变化 提供了在EM测试线上与金属挤压的预期位置紧密物理接近的位置。 一个或多个电容器中的每一个的电容在EM测试线之前和之后测量,以便检测指示金属挤压的电容变化。

    Noncontact electrical testing with optical techniques
    88.
    发明授权
    Noncontact electrical testing with optical techniques 失效
    用光学技术进行非接触式电气测试

    公开(公告)号:US08742782B2

    公开(公告)日:2014-06-03

    申请号:US13191555

    申请日:2011-07-27

    IPC分类号: G01R31/28

    CPC分类号: G01R31/31728

    摘要: An on-chip technique for noncontact electrical testing of a test structure on a chip is provided. On-chip photodiodes receives pump light from a pump light source, where the on-chip photodiodes are electrically connected to the test structure and are configured to generate power for the test structure. An on-chip coupling unit receives probe light from a probe light source, where the on-chip coupling unit is optically connected to on-chip waveguides through which the probe light is transferred. On-chip switches open in response to receiving voltage output from the test structure, and the on-chip switches remain closed when the voltage output is not received from the test structure. The on-chip switches pass the probe light when opened by the voltage output from the test structure. The on-chip switches block the probe light by remaining closed, when the voltage output is not received from the test structure.

    摘要翻译: 提供了芯片上测试结构的非接触电测试的片上技术。 片上光电二极管从泵浦光源接收泵浦光,其中片上光电二极管电连接到测试结构,并且被配置为产生用于测试结构的电力。 片上耦合单元接收来自探针光源的探测光,其中片上耦合单元光学连接到传输探针光的片上波导。 响应于测试结构的接收电压输出,片内开关打开,并且当没有从测试结构接收到电压输出时,片上开关保持闭合。 当由测试结构输出的电压打开时,片上开关通过探测灯。 当没有从测试结构接收到电压输出时,片内开关通过保持关闭来阻止探测光。

    ANTI-FUSE STRUCTURE AND FABRICATION
    90.
    发明申请
    ANTI-FUSE STRUCTURE AND FABRICATION 有权
    防冻结构和制造

    公开(公告)号:US20130307115A1

    公开(公告)日:2013-11-21

    申请号:US13475542

    申请日:2012-05-18

    IPC分类号: H01L23/52 H01L21/768

    摘要: A method and structure of a non-intrinsic anti-fuse structure. The anti-fuse structure has a first electrode, a second electrode, a first dielectric, and second dielectric. The first and second dielectrics have an interface which couples electrodes. The length along the interface which couples the electrodes is called the predetermined length. When the anti-fuse is programmed a conductive link forms along the interface to connect the first and second electrodes. The anti-fuse structure can be single-level or dual-level. The predetermined length can be less than spacing between adjacent electrodes when a dual-level structure is used. The anti-fuse structures have the advantage that they can be programmed at lower voltages than intrinsic structures and no extra steps are needed to integrate the anti-fuses with active structures.

    摘要翻译: 非本征反熔丝结构的方法和结构。 反熔丝结构具有第一电极,第二电极,第一电介质和第二电介质。 第一和第二电介质具有连接电极的界面。 沿着连接电极的界面的长度称为预定长度。 当反熔丝被编程时,沿着界面形成导电连接以连接第一和第二电极。 反熔丝结构可以是单级或双级。 当使用双层结构时,预定长度可以小于相邻电极之间的间距。 反熔丝结构具有的优点是可以以比内部结构更低的电压进行编程,并且不需要额外的步骤来将反熔丝与有源结构集成。