公开(公告)号：US08193526B2

公开(公告)日：2012-06-05

申请号：US12672135

申请日：2008-08-06

申请人： Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Kitae ,  Susumu Sawada

发明人： Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Kitae ,  Susumu Sawada

IPC分类号： H01L51/00

CPC分类号： H01L51/057 ,  H01L27/3274 ,  H01L27/3276 ,  H01L51/0096 ,  Y02E10/549 ,  Y02P70/521

摘要： A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided.A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, a source electrode disposed along the inner wall of the through hole, a drain electrode disposed along the inner wall of the through hole, a gate electrode disposed on the other surface of the resin film opposing the through hole, an insulating layer disposed on the gate electrode at the bottom of the through hole and an organic semiconductor disposed in the through hole so as to contact the source electrode and the drain electrode, wherein the organic semiconductor makes contact with at least a part of the insulating layer at the bottom of the through hole so that a channel is formed in the organic semiconductor in the vicinity of the insulating layer that is in contact therewith.

摘要翻译： 提供了具有以更高密度形成的半导体元件的半导体器件。 此外，还提供了使用该半导体器件的图像显示装置。 一种半导体器件，包括具有从一个表面到另一个表面穿透的通孔的树脂膜，沿着通孔的内壁设置的源电极，沿该通孔的内壁设置的漏电极， 设置在与通孔相对的树脂膜的另一个表面上的栅电极，设置在通孔底部的栅电极上的绝缘层和布置在通孔中的有机半导体，以便与源电极和漏极 电极，其中有机半导体与通孔底部的绝缘层的至少一部分接触，使得在与其接触的绝缘层附近的有机半导体中形成沟道。

公开(公告)号：US20080197173A1

公开(公告)日：2008-08-21

申请号：US11579505

申请日：2006-04-25

申请人： Takashi Kitae ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Yoshihisa Yamashita

发明人： Takashi Kitae ,  Seiichi Nakatani ,  Toshiyuki Kojima ,  Shingo Komatsu ,  Yoshihisa Yamashita

IPC分类号： B23K31/02 ,  B23K1/20

CPC分类号： H05K3/3484 ,  H01L21/4853 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/11003 ,  H01L2224/1152 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/81141 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/07811 ,  H01L2924/09701 ,  H01L2924/15787 ,  H01L2924/15788 ,  H05K3/323 ,  H05K3/3436 ,  H05K2201/09745 ,  H05K2201/10977 ,  H05K2203/0108 ,  H05K2203/0113 ,  H05K2203/043 ,  H05K2203/0465 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/29099

摘要： [Problem] To provide a method for forming solder bumps for realizing high density mounting and a highly reliable method for mounting a semiconductor device.[Means for Solving Problem] A flat plate 10 or 30 having a plurality of projections 12 or recesses 32 thereon is prepared; the flat plate is aligned to oppose an electronic component 14 or 34 and a resin composition 18 or 19 including a solder powder 22 or 23 is supplied to a gap between the flat plate and the electronic component; the resin composition is annealed to melt the solder powder included in the resin composition for growing the solder powder up to the level of the surface of the flat plate by allowing the melted solder powder to self-assemble on terminals 16 or 36, so as to form solder bumps 24 or 38 on the terminals; and the flat plate is removed after cooling and solidifying the solder bumps. Thus, the solder bumps 24 or 38 having pits 24a corresponding to the projections 12 or having projections 38a corresponding to the recesses 32 are formed.

摘要翻译： [问题]提供一种形成用于实现高密度安装的焊料凸块的方法和用于安装半导体器件的高可靠性方法。 [解决问题的手段]准备在其上具有多个突起12或凹部32的平板10或30; 平板对准电子部件14或34，并且包括焊料粉末22或23的树脂组合物18或19被供应到平板和电子部件之间的间隙; 对树脂组合物进行退火，通过使熔融的焊料粉末在端子16或36上自组装，将包含在用于生长焊料粉末的树脂组合物中的焊料粉末熔化至平板表面的高度，从而 在端子上形成焊料凸块24或38; 并且在冷却并固化焊料凸块之后去除平板。 因此，形成具有对应于突起12的凹坑24a或具有对应于凹部32的突起38a的焊料凸块24或38。

公开(公告)号：US08039307B2

公开(公告)日：2011-10-18

申请号：US12728615

申请日：2010-03-22

申请人： Toshiyuki Kojima ,  Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Kitae ,  Shingo Komatsu

发明人： Toshiyuki Kojima ,  Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Kitae ,  Shingo Komatsu

IPC分类号： H01L23/498

CPC分类号： H01L24/81 ,  H01L21/6835 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/17 ,  H01L24/24 ,  H01L24/25 ,  H01L24/45 ,  H01L24/48 ,  H01L24/82 ,  H01L24/83 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16058 ,  H01L2224/16059 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/171 ,  H01L2224/24011 ,  H01L2224/24225 ,  H01L2224/24226 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/82001 ,  H01L2224/83385 ,  H01L2224/83886 ,  H01L2224/83888 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01009 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19043 ,  H01L2924/3025 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/20752 ,  H01L2924/00015 ,  H01L2224/81805 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： A mounted body (100) of the present invention includes: a semiconductor element (10) having a surface (10a) on which element electrodes (12) are formed and a rear surface (10b) opposing the surface (10a); and a mounting board (30) on which wiring patterns (35) each having an electrode terminal (32) are formed. The rear surface (10b) of the semiconductor element (10) is in contact with the mounting board (30), and the element electrodes (12) of the semiconductor element (10) are connected electrically to the electrode terminals (32) of the wiring pattern (35) formed on the mounting board (30) via solder connectors (20) formed of solder particles assembled into a bridge shape. With this configuration, fine pitch connection between the element electrodes of the semiconductor element and the electrode terminals of the mounting board becomes possible.

摘要翻译： 本发明的安装体（100）包括：具有形成元件电极（12）的表面（10a）和与表面（10a）相对的后表面（10b）的半导体元件（10）。 以及安装板（30），在其上形成有各自具有电极端子（32）的布线图案（35）。 半导体元件（10）的后表面（10b）与安装板（30）接触，并且半导体元件（10）的元件电极（12）与电极端子（32）电连接 通过由组装成桥形的焊料颗粒形成的焊料连接器（20）在安装板（30）上形成的布线图案（35）。 利用这种结构，半导体元件的元件电极和安装板的电极端子之间的细间距连接成为可能。

公开(公告)号：US07977741B2

公开(公告)日：2011-07-12

申请号：US12939729

申请日：2010-11-04

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US07851281B2

公开(公告)日：2010-12-14

申请号：US12518602

申请日：2008-10-01

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L21/336

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US20100182144A1

公开(公告)日：2010-07-22

申请号：US12376661

申请日：2007-08-06

申请人： Yoshihisa Yamashita ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Fumio Fukushima ,  Kuniaki Kiyosue

发明人： Yoshihisa Yamashita ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Fumio Fukushima ,  Kuniaki Kiyosue

IPC分类号： G08B1/08 ,  G06K19/077 ,  G06K19/06 ,  B32B38/10

CPC分类号： H01Q19/10 ,  G06K19/07749 ,  G06K19/07771 ,  H01Q1/2208 ,  H01Q17/00

摘要： Provided is a RFID magnetic sheet to be attached to an IC tag. The RFID magnetic sheet is provided with a plurality of stripe arranged layers (11a, 11b) whereupon a plurality of magnetic stripes (12) composed of a metal magnetic material are arranged at intervals, and a resin film (10) interposed between the respective stripe arranged layers. The arrangement relationship between the stripe arranged layers is set so that the magnetic stripes on each of the stripe arranged layers intersect with the magnetic stripes on the other stripe arranged layer in a planar shape.

摘要翻译： 提供了要附接到IC标签的RFID磁性片。 RFID磁性片设置有多个条状布置层（11a，11b），由此间隔地布置由金属磁性材料构成的多个磁条（12），并且在相应条带之间插入树脂膜（10） 布置层。 设置条纹布置层之间的布置关系，使得每个条纹布置层上的磁条与另一个条纹布置层上的磁条以平面形状相交。

公开(公告)号：US20100012936A1

公开(公告)日：2010-01-21

申请号：US12518602

申请日：2008-10-01

申请人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

发明人： Koichi Hirano ,  Seiichi Nakatani ,  Shingo Komatsu ,  Yoshihisa Yamashita ,  Takashi Ichiryu

IPC分类号： H01L29/786 ,  H01L21/336 ,  H01L21/8234 ,  B32B3/02

CPC分类号： H01L51/0024 ,  H01L29/41733 ,  H01L29/66742 ,  H01L29/78603 ,  H01L51/0023 ,  H01L51/0097 ,  H01L51/0525 ,  H01L51/055 ,  H01L51/102 ,  Y10T428/24917

摘要： A layered film of a three-layer clad foil formed with a first metal layer 23, a second metal layer 25, and an inorganic insulating layer 35 interposed therebetween is prepared. After the second metal layer 25 is partially etched to form a gate electrode 20g, the first metal layer 23 is partially etched to form source/drain electrodes 20s, 20d in a region corresponding to the gate electrode 20g. A semiconductor layer 40 is then formed in contact with the source/drain electrodes 20s, 20d and on the gate electrode 20g with the inorganic insulating layer 35 interposed therebetween. The inorganic insulating layer 35 on the gate electrode 20g functions as a gate insulating film 30, and the semiconductor layer 40 between the source/drain electrodes 20s, 20d on the inorganic insulating layer 35 functions as a channel.

摘要翻译： 制备形成有第一金属层23，第二金属层25和介于其间的无机绝缘层35的三层复合箔的分层膜。 在第二金属层25被部分蚀刻以形成栅电极20g之后，第一金属层23被部分蚀刻以在对应于栅电极20g的区域中形成源/漏电极20s，20d。 然后，将半导体层40形成为与源极/漏极20s，20d接触并且在栅极电极20g上形成有绝缘层35。 栅电极20g上的无机绝缘层35用作栅极绝缘膜30，无机绝缘层35上的源/漏电极20s，20d之间的半导体层40用作沟道。

公开(公告)号：US07321496B2

公开(公告)日：2008-01-22

申请号：US11079316

申请日：2005-03-15

申请人： Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

发明人： Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

IPC分类号： H05K1/11 ,  H05K1/14

CPC分类号： H05K3/386 ,  H01L51/424 ,  H01L2924/0002 ,  H05K1/16 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0191 ,  H05K2201/0376 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

摘要： A flexible substrate comprises: a film; an insulating resin layer formed on each of a front face of the film and a rear face of the film, which rear face is opposite to the front face; a front-sided wiring pattern embedded in the insulating resin layer formed on the front face of the film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on the rear face of the film; and a via which is located between the front-sided wiring pattern and the rear-sided wiring pattern and serves to electrically interconnect the front-sided wiring pattern and the rear-sided wiring pattern, wherein the insulating resin layer formed on each of the front face and the rear face of the film is thicker than the film.

摘要翻译： 柔性基板包括：膜; 形成在所述膜的前表面和所述膜的后表面中的每一个上的绝缘树脂层，所述后表面与所述前表面相对; 嵌入到形成在膜的前表面上的绝缘树脂层中的前侧布线图案和嵌入在形成在膜的背面上的绝缘树脂层中的背面布线图案; 以及位于前侧布线图案和背面布线图案之间的通孔，用于将前侧布线图案和背面布线图案电连接，其中形成在每个正面上的绝缘树脂层 薄膜的表面和背面比薄膜厚。

公开(公告)号：US20050205294A1

公开(公告)日：2005-09-22

申请号：US11079316

申请日：2005-03-15

申请人： Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

发明人： Yoshihisa Yamashita ,  Toshio Fujii ,  Seiichi Nakatani ,  Takashi Ichiryu ,  Satoru Tomekawa ,  Hiroki Yabe

IPC分类号： H05K1/03 ,  H05K1/16 ,  H05K3/20 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46

CPC分类号： H05K3/386 ,  H01L51/424 ,  H01L2924/0002 ,  H05K1/16 ,  H05K3/20 ,  H05K3/4069 ,  H05K3/4614 ,  H05K2201/0191 ,  H05K2201/0376 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

摘要： A flexible substrate comprising: (i) a film; (ii) an insulating resin layer formed on each of a front face of said film and a rear face of said film which face is opposite to said front face; (iii) a front-sided wiring pattern embedded in the insulating resin layer formed on said front face of said film, and a rear-sided wiring pattern embedded in the insulating resin layer formed on said rear face of said film; and (iv) a via which is located between a front-sided wiring pattern and a rear-sided wiring pattern and serves to electrically connect between said front-sided wiring pattern and said rear-sided wiring pattern; wherein said insulating resin layer formed on each of said front face and said rear face of the said film is thicker than said film.

摘要翻译： 一种柔性基板，包括：（i）膜; （ii）形成在所述膜的前表面和所述膜的与所述前表面相对的表面的每一个上的绝缘树脂层; （iii）嵌入在所述膜的所述前表面上形成的绝缘树脂层中的前侧布线图案和嵌入在所述膜的所述背面上形成的绝缘树脂层中的背面布线图案; 以及（iv）位于前侧布线图案和背面布线图案之间的通孔，用于电连接在所述前侧布线图案和所述背面布线图案之间; 其中形成在所述膜的所述前表面和所述后表面的每一个上的所述绝缘树脂层比所述膜厚。

公开(公告)号：US08288778B2

公开(公告)日：2012-10-16

申请号：US12672127

申请日：2008-08-06

申请人： Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Kitae ,  Susumu Sawada

发明人： Seiichi Nakatani ,  Yoshihisa Yamashita ,  Takashi Kitae ,  Susumu Sawada

IPC分类号： H01L51/52

CPC分类号： H01L27/3274 ,  H01L27/283 ,  H01L27/3248 ,  H01L27/3276 ,  H01L51/0005 ,  H01L51/0558 ,  H01L2227/323

摘要： A semiconductor device having a semiconductor elements formed with higher density is provided. Furthermore an image display device using the semiconductor device is also provided.A semiconductor device comprising a resin film that has a through hole that penetrates from one surface to the other surface thereof, an organic semiconductor disposed inside the through hole, an insulating film on one end of the organic semiconductor, a gate electrode on the insulating film, a source electrode connected electrically to the other end of the organic semiconductor and a drain electrode connected electrically to the other end of the organic semiconductor.

摘要翻译： 提供了具有以更高密度形成的半导体元件的半导体器件。 此外，还提供了使用该半导体器件的图像显示装置。 一种半导体器件，包括具有从一个表面到另一个表面穿透的通孔的树脂膜，设置在所述通孔内的有机半导体，在所述有机半导体的一端上的绝缘膜，所述绝缘膜上的栅电极 与该有机半导体的另一端电连接的源电极和与该有机半导体的另一端电连接的漏电极。