公开(公告)号：US08159023B2

公开(公告)日：2012-04-17

申请号：US12692527

申请日：2010-01-22

申请人： Syotaro Ono ,  Wataru Saito ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

发明人： Syotaro Ono ,  Wataru Saito ,  Nana Hatano ,  Hiroshi Ohta ,  Miho Watanabe

IPC分类号： H01L29/00

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/66712 ,  H01L29/7397

摘要： A semiconductor device includes a semiconductor substrate of a first conductivity type, a first semiconductor region of the first conductivity type on the semiconductor substrate, and a plurality of second semiconductor regions of a second conductivity type disposed separately in the first semiconductor region. A difference between a charge quantity expressed by an integral value of a net activated doping concentration in the second semiconductor regions in the surface direction of the semiconductor substrate and a charge quantity expressed by an integral value of a net activated doping concentration in the first semiconductor region in the surface direction of the semiconductor substrate is always a positive quantity and becomes larger from the depth of the first junction plane to a depth of a second junction plane on an opposite side from the first junction plane.

摘要翻译： 半导体器件包括第一导电类型的半导体衬底，半导体衬底上的第一导电类型的第一半导体区域和分开设置在第一半导体区域中的多个第二导电类型的第二半导体区域。 由半导体衬底的表面方向上的第二半导体区域中的净活化掺杂浓度的积分值表示的电荷量与由第一半导体区域中的净活化掺杂浓度的积分值表示的电荷量之间的差异 在半导体基板的表面方向总是为正量，并且从第一接合面的深度到与第一接合面相反的一侧的第二接合面的深度变得更大。

公开(公告)号：US20120068258A1

公开(公告)日：2012-03-22

申请号：US13052908

申请日：2011-03-21

申请人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Syotaro ONO ,  Wataru Saito ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7811 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/84 ,  H01L29/0619 ,  H01L29/402 ,  H01L29/42372 ,  H01L29/66712 ,  H01L2224/37013 ,  H01L2224/40245 ,  H01L2224/40479 ,  H01L2224/40499 ,  H01L2224/4103 ,  H01L2224/84203 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/37099

摘要： According to one embodiment, a semiconductor device includes a first main electrode, a control electrode, an extraction electrode, a second insulating film, a plurality of contact electrodes, and a control terminal. The first main electrode is electrically connected to a first semiconductor region of a first conductivity type and a second semiconductor region of a second conductivity type selectively provided on a surface of the first semiconductor region. The control electrode is provided on the first semiconductor region via a first insulating film. The extraction electrode is electrically connected to the control electrode. The second insulating film is provided on the first main electrode and the extraction electrode. The plurality of contact electrodes are provided in an inside of a plurality of first contact holes formed in the second insulating film and are electrically connected to the extraction electrode. The control terminal covers portions of the first main electrode provided on the first semiconductor region, on the second semiconductor region, and on the control electrode, respectively, and the extraction electrode, is electrically connected to the plurality of contact electrodes, and is electrically insulated from the first main electrode by the second insulating film.

摘要翻译： 根据一个实施例，半导体器件包括第一主电极，控制电极，引出电极，第二绝缘膜，多个接触电极和控制端子。 第一主电极电连接到第一导电类型的第一半导体区域和选择性地设置在第一半导体区域的表面上的第二导电类型的第二半导体区域。 控制电极经由第一绝缘膜设置在第一半导体区域上。 引出电极与控制电极电连接。 第二绝缘膜设置在第一主电极和引出电极上。 多个接触电极设置在形成在第二绝缘膜中的多个第一接触孔的内部，并与引出电极电连接。 控制端子分别覆盖设置在第一半导体区域上，第二半导体区域上和控制电极上的第一主电极的部分，并且引出电极电连接到多个接触电极，并且是电绝缘的 从第一主电极通过第二绝缘膜。

公开(公告)号：US08125023B2

公开(公告)日：2012-02-28

申请号：US12620045

申请日：2009-11-17

申请人： Hiroshi Ohta ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

发明人： Hiroshi Ohta ,  Wataru Saito ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Nana Hatano ,  Miho Watanabe

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/41741 ,  H01L29/7395 ,  H01L29/7811 ,  Y10S257/901

摘要： In a vertical power semiconductor device having the super junction structure both in a device section and a terminal section, an n-type impurity layer is formed on the outer peripheral surface in the super junction structure. This allows an electric field on the outer peripheral surface of the super junction structure region to be reduced. Accordingly, a reliable vertical power semiconductor device of a high withstand voltage can be provided.

摘要翻译： 在器件部分和端子部分都具有超结结构的垂直功率半导体器件中，在超结结构的外周表面上形成n型杂质层。 这允许减小超结结构区域的外周表面上的电场。 因此，可以提供高耐受电压的可靠的垂直功率半导体器件。

公开(公告)号：US20120015402A1

公开(公告)日：2012-01-19

申请号：US13187677

申请日：2011-07-21

申请人： Masayuki Tsuchiya ,  Masami Suzuki ,  Kenji Yoshida ,  Etsuko Fujii ,  Miho Watanabe ,  Koichi Matsubara ,  Yu Jau Chen ,  Juliana Sim

发明人： Masayuki Tsuchiya ,  Masami Suzuki ,  Kenji Yoshida ,  Etsuko Fujii ,  Miho Watanabe ,  Koichi Matsubara ,  Yu Jau Chen ,  Juliana Sim

IPC分类号： C12P21/00 ,  C12N5/071

CPC分类号： A01K67/027 ,  A01K2267/01 ,  A61K35/16 ,  C07K16/00 ,  C07K16/30

摘要： An objective of the present invention is to facilitate the acquisition of antibody-producing cells that are infiltrating virus-infected cells, cancer cells, abnormal cells forming a benign hyperplasia, and the like, and to improve the efficiency of the production of antibodies as well as nucleic acids encoding them from the antibody-producing cells.The present inventors discovered that, when cancer tissues comprising infiltrating lymphocytes are transplanted into highly immunodeficient animals that do not have T cells, B cells, and NK cells and further exhibit a low IFN production ability, the differentiation and proliferation of infiltrating lymphocytes are unexpectedly promoted, and the number of plasma cells that produce antibodies recognizing cancer tissues increases dramatically, plasma cells can be separated easily, and antibodies or nucleic acids encoding them can be easily prepared from the plasma cells.

摘要翻译： 本发明的目的是便于获得渗透病毒感染细胞的抗体产生细胞，癌细胞，形成良性增生的异常细胞等，以及提高抗体生产的效率 作为从抗体产生细胞编码它们的核酸。 本发明人发现，当将包含浸润性淋巴细胞的癌组织移植到不具有T细胞，B细胞和NK细胞的高度免疫缺陷的动物中并且进一步表现出低的IFN产生能力时，意外地促进了浸润性淋巴细胞的分化和增殖 并且产生识别癌组织的抗体的浆细胞的数量急剧增加，可以容易地分离浆细胞，并且可以容易地从浆细胞制备抗体或编码它们的核酸。

公开(公告)号：US08030706B2

公开(公告)日：2011-10-04

申请号：US12540192

申请日：2009-08-12

申请人： Miho Watanabe ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Nana Hatano

发明人： Miho Watanabe ,  Masaru Izumisawa ,  Yasuto Sumi ,  Hiroshi Ohta ,  Wataru Sekine ,  Wataru Saito ,  Syotaro Ono ,  Nana Hatano

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/7802

摘要： A semiconductor device according to an embodiment of the present invention includes a device part and a terminal part. The device includes a first semiconductor layer, and second and third semiconductor layers formed on the first semiconductor layer, and alternately arranged along a direction parallel to a surface of the first semiconductor layer, wherein the device part is provided with a first region and a second region, each of which includes at least one of the second semiconductor layers and at least one of the third semiconductor layers, and with regard to a difference value ΔN (=NA−NB) obtained by subtracting an impurity amount NB per unit length of each of the third semiconductor layers from an impurity amount NA per unit length of each of the second semiconductor layers, a difference value ΔNC1 which is the difference value ΔN in the first region of the device part, a difference value ΔNC2 which is the difference value ΔN in the second region of the device part, and a difference value ΔNT which is the difference value ΔN in the terminal part satisfy a relationship of ΔNC1>ΔNT>ΔNC2.

摘要翻译： 根据本发明实施例的半导体器件包括器件部分和端子部分。 该器件包括第一半导体层，以及形成在第一半导体层上的第二和第三半导体层，并且沿着与第一半导体层的表面平行的方向交替布置，其中器件部分设置有第一区域和第二半导体层 区域，其中每一个包括第二半导体层和至少一个第三半导体层中的至少一个，并且关于通过从每单位长度减去杂质量NB获得的差值Dgr; N（= NA-NB） 从每个第二半导体层的每单位长度的杂质量NA中的每个第三半导体层的差分值＆Dgr; NC1，其是器件部分的第一区域中的差值＆Dgr; N，差值＆Dgr ;作为装置部分的第二区域中的差值Dgr; N的NC2，作为终端部分中的差值Dgr; N的差值＆Dgr; NT满足关系 的＆Dgr; NC1>＆Dgr; NT>＆Dgr; NC2。

公开(公告)号：US20110227154A1

公开(公告)日：2011-09-22

申请号：US13052032

申请日：2011-03-18

申请人： Syotaro ONO ,  Wataru Saito ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

发明人： Syotaro ONO ,  Wataru Saito ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/66712

摘要： A semiconductor device comprising: a first semiconductor layer of a first conductivity type; a second semiconductor layer of the first conductivity type formed on the first semiconductor layer; a first buried layer of the first conductivity type selectively formed in the second semiconductor layer and having a first peak impurity concentration at a first depth; a second buried layer of a second conductivity type selectively formed in the second semiconductor layer and having a second peak impurity concentration at a second depth; a base layer of the second conductivity type selectively formed in the second semiconductor layer and overlapping with an upper portion of the second buried layer; a source layer of the first conductivity type selectively formed in the base layer; and a gate electrode formed on the base layer and on the second semiconductor layer above the first buried layer with a gate insulating film being interposed therebetween.

摘要翻译： 一种半导体器件，包括：第一导电类型的第一半导体层; 形成在第一半导体层上的第一导电类型的第二半导体层; 第一导电类型的第一掩埋层选择性地形成在第二半导体层中，并且在第一深度处具有第一峰值杂质浓度; 第二导电类型的第二掩埋层选择性地形成在第二半导体层中，并且在第二深度具有第二峰值杂质浓度; 第二导电类型的基极层选择性地形成在第二半导体层中并与第二掩埋层的上部重叠; 选择性地形成在所述基底层中的所述第一导电类型的源极层; 以及形成在所述第一掩埋层上的所述基极层和所述第二半导体层上的栅电极，其间插入有栅极绝缘膜。

公开(公告)号：US20110215418A1

公开(公告)日：2011-09-08

申请号：US13029925

申请日：2011-02-17

申请人： Wataru SAITO ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

发明人： Wataru SAITO ,  Syotaro Ono ,  Munehisa Yabuzaki ,  Shunji Taniuchi ,  Miho Watanabe

IPC分类号： H01L27/07 ,  H01L29/72

CPC分类号： H01L27/07 ,  H01L29/72

摘要： According to one embodiment, a semiconductor device includes a first semiconductor region of a first conductivity type, a second semiconductor region of the first conductivity type, a first main electrode, a third semiconductor region of a second conductivity type, a second main electrode, and a plurality of embedded semiconductor regions of the second conductivity type. The second semiconductor region is formed on a first major surface of the first semiconductor region. The first main electrode is formed on a face side opposite to the first major surface of the first semiconductor region. The third semiconductor region is formed on a second major surface of the second semiconductor region on a side opposite to the first semiconductor region. The second main electrode is formed to bond to the third semiconductor region. The embedded semiconductor regions are provided in a termination region. A distance between the embedded semiconductor region and the second major surface along a direction from the second major surface toward the first major surface becomes longer toward outside from the device region.

摘要翻译： 根据一个实施例，半导体器件包括第一导电类型的第一半导体区域，第一导电类型的第二半导体区域，第一主电极，第二导电类型的第三半导体区域，第二主电极和 多个第二导电类型的嵌入式半导体区域。 第二半导体区域形成在第一半导体区域的第一主表面上。 第一主电极形成在与第一半导体区域的第一主表面相对的正面上。 第三半导体区域形成在第二半导体区域的与第一半导体区域相对的一侧的第二主表面上。 第二主电极形成为结合到第三半导体区域。 嵌入式半导体区域设置在终端区域中。 沿着从第二主表面朝向第一主表面的方向在嵌入式半导体区域和第二主表面之间的距离从器件区域向外部变长。

公开(公告)号：US20080070142A1

公开(公告)日：2008-03-20

申请号：US11704989

申请日：2007-02-12

申请人： Makoto Furuki ,  Minquan Tian ,  Miho Watanabe ,  Takashi Matsubara

发明人： Makoto Furuki ,  Minquan Tian ,  Miho Watanabe ,  Takashi Matsubara

IPC分类号： G03G9/08

CPC分类号： G03G9/0918 ,  G03G9/0926

摘要： The invention provides a toner for electrostatic charge development including a binder resin and an infrared absorber, wherein at least one of the infrared absorbers is a compound represented by Structural Formula (1).

摘要翻译： 本发明提供一种用于静电荷显影的调色剂，包括粘合剂树脂和红外吸收剂，其中至少一种红外线吸收剂是由结构式（1）表示的化合物。

公开(公告)号：US08678618B2

公开(公告)日：2014-03-25

申请号：US12885849

申请日：2010-09-20

申请人： Makoto Sakai ,  Masao Segawa ,  Nobuo Shibano ,  Kiyoshi Nishimura ,  Kozo Ogawa ,  Masahiko Kamata ,  Toshiya Tanaka ,  Miho Watanabe ,  Shuhei Matsuda

发明人： Makoto Sakai ,  Masao Segawa ,  Nobuo Shibano ,  Kiyoshi Nishimura ,  Kozo Ogawa ,  Masahiko Kamata ,  Toshiya Tanaka ,  Miho Watanabe ,  Shuhei Matsuda

IPC分类号： F21V29/00

CPC分类号： F21V29/507 ,  F21K9/232 ,  F21V3/04 ,  F21V29/506 ,  F21V29/89 ,  F21Y2107/00 ,  F21Y2107/40 ,  F21Y2115/10

摘要： A self-ballasted lamp includes: a base body; a light-emitting module and a globe which are provided at one end side of the base body; a cap provided at the other end side of the base body; and a lighting circuit housed between the base body and the cap. The light-emitting module has light-emitting portions each using a semiconductor light-emitting element, and a support portion projected at one end side of the base body, and the light-emitting portions are disposed at least on a circumferential surface of the support portion. A light-transmissive member is interposed between the light-emitting module and an inner face of the globe.

摘要翻译： 自镇流灯包括：基体; 发光模块和球体，其设置在所述基体的一端侧; 设置在所述基体的另一端侧的盖; 以及容纳在基体和盖之间的照明电路。 发光模块具有各自使用半导体发光元件的发光部和在基体的一端侧突出的支撑部，发光部至少设置在支撑体的周面上 一部分。 在发光模块和球体的内表面之间插入透光构件。

公开(公告)号：US08643091B2

公开(公告)日：2014-02-04

申请号：US13052028

申请日：2011-03-18

申请人： Wataru Saito ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

发明人： Wataru Saito ,  Syotaro Ono ,  Shunji Taniuchi ,  Miho Watanabe ,  Hiroaki Yamashita

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7839 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/407 ,  H01L29/41741 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7806 ,  H01L29/7811 ,  H01L29/7813

摘要： A semiconductor device includes first, second, third, and fourth semiconductor layers of alternating first and second conductivity types, an embedded electrode in a first trench that penetrates through the second semiconductor layer, a control electrode above the embedded electrode in the first trench, and first and second main electrodes. The fourth semiconductor layer is selectively provided in the first semiconductor layer and is connected to a lower end of a second trench, which penetrates through the second semiconductor layer. The first main electrode is electrically connected to the first semiconductor layer, and the second main electrode is in the second trench and electrically connected to the second, third, and fourth semiconductor layers. The embedded electrode is electrically connected to the second main electrode or the control electrode. A Shottky junction formed of the second main electrode and the first semiconductor layer is formed at a sidewall of the second trench.

摘要翻译： 半导体器件包括交替的第一和第二导电类型的第一，第二，第三和第四半导体层，穿透第二半导体层的第一沟槽中的嵌入电极，在第一沟槽中的嵌入电极上方的控制电极，以及 第一和第二主电极。 第四半导体层选择性地设置在第一半导体层中，并且连接到穿过第二半导体层的第二沟槽的下端。 第一主电极与第一半导体层电连接，第二主电极位于第二沟槽中，并与第二，第三和第四半导体层电连接。 嵌入电极与第二主电极或控制电极电连接。 在第二沟槽的侧壁处形成由第二主电极和第一半导体层形成的肖特基结。