公开(公告)号：US08149619B2

公开(公告)日：2012-04-03

申请号：US13026052

申请日：2011-02-11

申请人： Howard C. Kirsch ,  Charles Ingalls ,  Werner Juengling

发明人： Howard C. Kirsch ,  Charles Ingalls ,  Werner Juengling

IPC分类号： G11C14/00

CPC分类号： G11C14/0018 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.

摘要翻译： 提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。 有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。 提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分的非易失性存储器部分 行的存储单元。

公开(公告)号：US08111570B2

公开(公告)日：2012-02-07

申请号：US12906806

申请日：2010-10-18

申请人： Tae Kim ,  Howard C. Kirsch

发明人： Tae Kim ,  Howard C. Kirsch

IPC分类号： G11C7/00

CPC分类号： G11C7/08 ,  G11C7/062

摘要： Embodiments are described for a voltage compensated sense amplifier. One such sense amplifier includes a pair of digit line nodes respectively coupled to a pair of transistors. A first pair of switches are adapted to cross-couple the gates of the transistors to the respective digit line node and a second pair of switches are adapted to couple the gates of the transistors to a voltage supply. The first and second pair of switches are coupled to respective gates of the transistors independent of the pair of transistors being respectively coupled to the digit line nodes.

摘要翻译： 针对电压补偿的读出放大器描述实施例。 一个这样的感测放大器包括分别耦合到一对晶体管的一对数字线节点。 第一对开关适于将晶体管的栅极交叉耦合到相应的数字线节点，并且第二对开关适于将晶体管的栅极耦合到电压源。 第一和第二对开关耦合到晶体管的相应栅极，独立于一对晶体管分别耦合到数字线节点。

公开(公告)号：US20110304358A1

公开(公告)日：2011-12-15

申请号：US12815176

申请日：2010-06-14

申请人： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

发明人： J. Wayne Thompson ,  Howard C. Kirsch ,  Charles L. Ingalls

IPC分类号： H03F3/45

CPC分类号： G11C7/12 ,  G11C7/06 ,  G11C7/065 ,  G11C11/4091 ,  G11C11/4094

摘要： Sense amplifiers and methods for precharging are disclosed, including a sense amplifier having a pair of cross-coupled complementary transistor inverters, and a pair of transistors, each one of the pair of transistors coupled to a respective one of the complementary transistor inverters and a voltage. The sense amplifier further includes a capacitance coupled between the pair of transistors. One method for precharging includes coupling input nodes of the sense amplifier to a precharge voltage, coupling the input nodes of the sense amplifier together, and coupling a resistance to each transistor of a cross-coupled pair to set a voltage threshold (VT) mismatch compensation voltage for each transistor. The voltage difference between the VT mismatch compensation voltage of each transistor is stored.

摘要翻译： 公开了用于预充电的感测放大器和方法，包括具有一对交叉耦合的互补晶体管反相器的读出放大器和一对晶体管，耦合到互补晶体管反相器中的相应一个的一对晶体管中的每一个， 。 感测放大器还包括耦合在该对晶体管之间的电容。 一种用于预充电的方法包括将读出放大器的输入节点耦合到预充电电压，将读出放大器的输入节点耦合在一起，并将电阻耦合到交叉耦合对的每个晶体管，以设置电压阈值（VT）失配补偿 每个晶体管的电压。 存储每个晶体管的VT失配补偿电压之间的电压差。

公开(公告)号：US07898857B2

公开(公告)日：2011-03-01

申请号：US12052300

申请日：2008-03-20

申请人： Howard C. Kirsch ,  Charles Ingalls ,  Werner Juengling

发明人： Howard C. Kirsch ,  Charles Ingalls ,  Werner Juengling

IPC分类号： G11C16/04

CPC分类号： G11C14/0018 ,  G11C16/0466 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10826 ,  H01L27/10876 ,  H01L27/10894 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

摘要： A memory array is provided that includes a transistor having two active gates sharing a source, a drain, and a channel of the transistor. One of the active gates may be coupled to a volatile memory portion of a memory cell, such as a DRAM cell, and the other active gate may be coupled to a non-volatile memory portion, for example, a charge storage node such as a SONOS cell. Methods of operating the memory array are provided that include transferring data from the volatile memory portions to the non-volatile memory portions, transferring data from the non-volatile memory portions to the volatile memory portions, and erasing the non-volatile memory portions of a row of memory cells.

摘要翻译： 提供一种存储器阵列，其包括具有共享晶体管的源极，漏极和沟道的两个有源栅极的晶体管。 有源栅极中的一个可以耦合到诸如DRAM单元的存储器单元的易失性存储器部分，并且另一有源栅极可以耦合到非易失性存储器部分，例如电荷存储节点，例如 SONOS细胞。 提供了操作存储器阵列的方法，其包括将数据从易失性存储器部分传送到非易失性存储器部分，将数据从非易失性存储器部分传送到易失性存储器部分，以及擦除非易失性存储器部分的非易失性存储器部分 行的存储单元。

公开(公告)号：US07277310B2

公开(公告)日：2007-10-02

申请号：US11501144

申请日：2006-08-07

申请人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

发明人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

IPC分类号： G11C5/06

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

摘要翻译： 一种用于感测由存储器单元存储的数据状态的系统和方法，包括将第一数字线和第二数字线耦合到预充电电压，并进一步将存储单元耦合到第一数字线。 除了第一和第二数字线之外的至少一个数字线被驱动到参考电压电平，并且至少一个数字线耦合到第二数字线以在第二数字线中建立参考电压。 在第一数字线和第二数字线之间感测到电压差，并且响应地锁存基于电压差的数据状态。

公开(公告)号：US07193914B2

公开(公告)日：2007-03-20

申请号：US11500786

申请日：2006-08-07

申请人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

发明人： Sei Seung Yoon ,  Charles L. Ingalls ,  David Pinney ,  Howard C. Kirsch

IPC分类号： G11C7/00

CPC分类号： G11C7/18 ,  G11C7/04 ,  G11C7/065 ,  G11C7/12 ,  G11C7/14 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

摘要： A system and method for sensing a data state stored by a memory cell that includes coupling a first digit line and a second digit line to a precharge voltage and further coupling a memory cell to the first digit line. At least one digit line other than the first and second digit lines is driven to a reference voltage level and the at least one digit line is coupled to the second digit line to establish a reference voltage in the second digit line. A voltage differential is sensed between the first digit line and the second digit line, and a data state based on the voltage differential is latched in response.

公开(公告)号：US07170124B2

公开(公告)日：2007-01-30

申请号：US10968429

申请日：2004-10-19

申请人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

发明人： Luan C. Tran ,  Mark Durcan ,  Howard C. Kirsch

IPC分类号： H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10814 ,  H01L27/10888

摘要： A memory device includes isolation trenches that are formed generally parallel to and along associated strips of active area. A conductive bit line is recessed within each isolation trench such that the uppermost surface of the bit line is recessed below the uppermost surface of the base substrate. A bit line contact strap electrically couples the bit line to the active area both along a vertical dimension of the bit line strap and along a horizontal dimension across the uppermost surface of the base substrate.

公开(公告)号：US06727740B2

公开(公告)日：2004-04-27

申请号：US10232475

申请日：2002-08-29

申请人： Howard C. Kirsch

发明人： Howard C. Kirsch

IPC分类号： H03L700

CPC分类号： G11C7/222 ,  G11C7/22 ,  H03K5/135 ,  H03L7/00

摘要： A synchronous mirror delay includes a ring oscillator that generates a plurality of tap clock signals with one tap clock signal being designated an oscillator clock signal. In response to an input clock signal, a model delay line generates a model delayed clock signal having a model delay relative to the input clock signal. A coarse delay circuit generates a coarse delay count responsive to the oscillator, input, and model delayed clock signals, and activates a coarse delay enable signal responsive to the delay count being equal to a reference count value. A fine delay circuit latches the tap clock signals and develops a fine delay from the latched signals, and activates a fine delay enable signal having the fine delay in response to the coarse delay enable signal. An output circuit generates a delayed clock signal responsive to the coarse and fine delay enable signals going active.

摘要翻译： 同步镜延迟包括环形振荡器，其产生多个抽头时钟信号，其中一个抽头时钟信号被指定为振荡器时钟信号。 响应于输入时钟信号，模型延迟线产生具有相对于输入时钟信号的模型延迟的模型延迟时钟信号。 粗延迟电路响应于振荡器，输入和模型延迟的时钟信号产生粗延迟计数，并且响应于延迟计数等于参考计数值而激活粗延迟使能信号。 精细延迟电路锁存分接时钟信号并从锁存信号产生精细延迟，并且响应于粗延迟使能信号激活具有精细延迟的精细延迟使能信号。 输出电路响应于粗略和精细的延迟使能信号变为有效而产生延迟的时钟信号。

公开(公告)号：US06621316B1

公开(公告)日：2003-09-16

申请号：US10176865

申请日：2002-06-20

申请人： Howard C. Kirsch

发明人： Howard C. Kirsch

IPC分类号： H03L700

CPC分类号： H03L7/0814 ,  H03K5/135

摘要： A synchronous mirror delay (SMD)includes a model delay line that is coupled to a bi-directional delay line. In operation, an initial edge an input clock signal is applied through the model delay line to the bi-directional delay line. The SMD thereafter operates in a forward delay mode to alternately operate the bi-directional delay line in a forward mode and a backward mode to propagate the initial edge of the input clock signal through the bi-directional delay line and delay the initial edge of the input clock signal by a forward delay. In response to a subsequent edge of the input clock signal, the SMD mirrors the propagation of the input clock signal through the bi-directional delay line during the forward mode and further delay the initial edge of the input clock signal by a backward delay that is substantially equal to the forward delay.

摘要翻译： 同步镜延迟（SMD）包括耦合到双向延迟线的模型延迟线。 在操作中，初始边沿通过模型延迟线将输入时钟信号施加到双向延迟线。 此后，SMD工作在正向延迟模式下，以正向模式和反向模式交替操作双向延迟线，以通过双向延迟线传播输入时钟信号的初始边沿，并延迟其中的初始边沿 通过正向延迟输入时钟信号。 响应于输入时钟信号的后续边沿，SMD在正向模式期间反射输入时钟信号通过双向延迟线的传播，并且进一步延迟输入时钟信号的初始边沿反向延迟 基本上等于前向延迟。

公开(公告)号：US06408264B1

公开(公告)日：2002-06-18

申请号：US09274211

申请日：1999-03-23

申请人： Jason Tzu-Jung Su ,  Howard C. Kirsch ,  Lidong Chen

发明人： Jason Tzu-Jung Su ,  Howard C. Kirsch ,  Lidong Chen

IPC分类号： G06F1750

CPC分类号： G06F17/5022

摘要： A switch level simulation system includes a netlister, a cross-coupled device detector, a cross-coupled device transformer and a switch level simulator. The user provides a circuit a design to the netlister, which generates a netlist of the circuit. The cross-coupled device detector searches the netlist to find all of the cross-coupled devices in the circuit design. The cross-coupled device detector also determines whether the cross-coupled device has a “rail” node directly connected an external voltage source line. The cross-coupled device transformer transforms each cross-coupled device having a rail node into a transformed cross-coupled device by inserting in the netlist a device at the rail node mirroring the enable device. The mirror device allows the transformed cross-coupled device to provide a high impedance state to emulate the meta-stable state of the cross-coupled device during switch level simulation. The switch level simulator then performs simulations using the netlist with the transformed cross-coupled devices. This technique avoids the need to construct behavioral models of the cross-coupled devices, significantly reducing the engineering resources needed to model cross-coupled devices, while maintaining the accuracy of the switch level simulation.

摘要翻译： 开关级仿真系统包括网络管理器，交叉耦合器件检测器，交叉耦合器件变压器和开关级仿真器。 用户向netlister提供电路设计，其产生电路的网表。 交叉耦合器件检测器搜索网表以查找电路设计中的所有交叉耦合器件。 交叉耦合器件检测器还确定交叉耦合器件是否具有直接连接外部电压源线的“导轨”节点。 交叉耦合器件变压器将具有轨道节点的每个交叉耦合器件变换成变换的交叉耦合器件，通过在网络表中插入镜像启用器件的轨道节点上的器件。 反射镜装置允许变换的交叉耦合器件提供高阻抗状态以在开关级仿真期间模拟交叉耦合器件的元稳定状态。 开关级仿真器然后使用具有变换的交叉耦合器件的网表进行仿真。 该技术避免了构建交叉耦合器件的行为模型，大大降低了交叉耦合器件建模所需的工程资源，同时保持了开关级仿真的准确性。