公开(公告)号：US20170085883A1

公开(公告)日：2017-03-23

申请号：US15367378

申请日：2016-12-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Hrushikesh Tukaram Garud ,  Mihir Narendra Mody ,  Soyeb Nagori

IPC: H04N19/147 ,  H04N19/82 ,  H04N19/149 ,  H04N19/182 ,  H04N19/176

CPC classification number: H04N19/147 ,  H04N19/117 ,  H04N19/149 ,  H04N19/176 ,  H04N19/182 ,  H04N19/82

Abstract: The disclosure provides a sample adaptive offset (SAO) encoder. The SAO encoder includes a statistics collection (SC) block and a rate distortion optimization (RDO) block coupled to the SC block. The SC block receives a set of deblocked pixels and a set of original pixels. The SC block categorizes each deblocked pixel of the set of deblocked pixels in at least one of a plurality of band and edge categories. The SC block estimates an error in each category as difference between a deblocked pixel of the set of deblocked pixels and corresponding original pixel of the set of original pixels. The RDO block determines a set of candidate offsets associated with each category and selects a candidate offset with a minimum RD cost. The minimum RD cost is used by a SAO type block and a decision block to generate final offsets for the SAO encoder.

公开(公告)号：US20150010052A1

公开(公告)日：2015-01-08

申请号：US14320712

申请日：2014-07-01

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Hrushikesh Tukaram Garud ,  Soyeb Nagori

IPC: H04N19/117 ,  H04N19/119 ,  H04N19/89 ,  H04N19/44 ,  H04N19/80 ,  H04N19/132 ,  H04N19/176

CPC classification number: H04N19/176 ,  H04N19/117 ,  H04N19/119 ,  H04N19/132 ,  H04N19/14 ,  H04N19/82

Abstract: An apparatus for sample adaptive offset (SAO) filtering in video encoding. A unified processing engine collects statistics on a block of pixels, determines a minimum RD cost (J) for each category of band offsets and edge offsets; determines a RD cost to find the optimal SAO type and determines a cost for each of the left SAO parameters and the up SAO parameters. The unified processing engine operates for three iterations: once for luminance once for each chrominance. A SAO merge decision unit determines an optimal mode and generates current LCU Parameters. The RD offset unit determination includes determining whether the sign of the minimum offset is proper for the category of edge offset. The RD offset is determined using a programmable look-up table indexed by the offset to estimate a rate. The unified processing engine operates on a three stage pipeline: loading blocks; processing; and updating blocks.

Abstract translation: 一种用于视频编码中采样自适应偏移（SAO）滤波的装置。 一个统一的处理引擎收集一个像素块的统计信息，确定每个类别的带偏移和边缘偏移量的最小RD成本（J）; 确定RD成本以找到最佳SAO类型，并确定每个左侧SAO参数和上升SAO参数的成本。 统一的处理引擎运行三次迭代：对于每个色度，亮度一次。 SAO合并决策单元确定最优模式并生成当前的LCU参数。 RD偏移单元确定包括确定最小偏移的符号是否适合于边缘偏移的类别。 使用由偏移量索引的可编程查找表来确定RD偏移以估计速率。 统一处理引擎在三级管道上运行：装载块; 加工; 和更新块。

公开(公告)号：US20140355691A1

公开(公告)日：2014-12-04

申请号：US14294711

申请日：2014-06-03

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody

IPC: H04N19/436 ,  H04N19/174 ,  H04N19/44

CPC classification number: H04N19/174 ,  H04N19/436

Abstract: A video hardware engine with multi-threading functionality is disclosed. The video hardware engine includes a video hardware accelerator unit and a controller. The controller is coupled to the video hardware accelerator unit. The controller operates in an encode mode and a decode mode. In the encode mode, the controller receives a plurality of frames and encode attributes associated with each frame of the plurality of frames. The encode attributes associated with a frame of the plurality of frames is processed to generate encode parameters associated with the frame. The video hardware accelerator unit is configured to process the frame based on the encode parameters to generate an output. The output of the video hardware accelerator unit is processed to generate a compressed bit-stream and an encode status. In decode mode, the controller receives a compressed bit-stream and decode attributes and generates a plurality of frames and a decode status.

Abstract translation: 公开了具有多线程功能的视频硬件引擎。 视频硬件引擎包括视频硬件加速器单元和控制器。 控制器耦合到视频硬件加速器单元。 控制器以编码模式和解码模式工作。 在编码模式中，控制器接收多个帧并编码与多个帧中的每个帧相关联的属性。 处理与多个帧的帧相关联的编码属性以生成与该帧相关联的编码参数。 视频硬件加速器单元被配置为基于编码参数处理帧以生成输出。 处理视频硬件加速器单元的输出以产生压缩比特流和编码状态。 在解码模式下，控制器接收压缩比特流并解码属性，并产生多个帧和解码状态。

公开(公告)号：US20140341287A1

公开(公告)日：2014-11-20

申请号：US14279318

申请日：2014-05-16

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Niraj Nandan ,  Hideo Tamama

IPC: H04N19/61 ,  H04N19/80

CPC classification number: H04N19/436 ,  H04N19/117 ,  H04N19/14 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/423 ,  H04N19/82

Abstract: A method for sample adaptive offset (SAO) filtering of largest coding units (LCUs) of a video frame in an SAO component is provided that includes receiving, by the SAO component, an indication that deblocked pixel blocks of an LCU are available, and applying SAO filtering, by the SAO component, to each pixel block of pixel blocks of an SAO processing area corresponding to the LCU responsive to the indication, wherein pixels of each pixel block of the SAO processing area are filtered in parallel.

Abstract translation: 提供了一种用于在SAO组件中的视频帧的最大编码单元（LCU）的采样自适应偏移（SAO）滤波的方法，其包括由SAO组件接收到LCU的解块像素块可用的指示，以及应用 通过SAO分量对SAO处理区域的对应于该LCU的SAO处理区域的每个像素块进行SAO滤波，其中SAO处理区域的每个像素块的像素被并行地滤波。

公开(公告)号：US12236562B2

公开(公告)日：2025-02-25

申请号：US18465250

申请日：2023-09-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Gang Hua ,  Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody

IPC: G06T5/80 ,  G06T3/18 ,  G06T7/60 ,  G06T11/40

Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.

公开(公告)号：US12185007B2

公开(公告)日：2024-12-31

申请号：US18091798

申请日：2022-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Niraj Nandan ,  Mihir Narendra Mody ,  Rajasekhar Allu

IPC: H04N25/77 ,  H04N23/698 ,  H04N23/81

Abstract: In an example, a method includes receiving image data of an input image having lines therein. The method also includes storing a first portion of the image data in a circular buffer in a first memory, wherein the first portion begins at a circular buffer start line in the input image and ends at a circular buffer end line in the input image. The method includes storing a second portion of the image data in a linear buffer in a second memory, where the second portion is non-overlapping with the first portion. The method includes processing the second portion of the image data to produce a first block of an output image. The method includes processing the first portion of the image data to produce a second block of the output image.

公开(公告)号：US20240420275A1

公开(公告)日：2024-12-19

申请号：US18816153

申请日：2024-08-27

Applicant: Texas Instruments Incorporated

Inventor： Hrushikesh Tukaram Garud ,  Ankit Ajmani ,  Soyeb Noormohammed Nagori ,  Mihir Narendra Mody

IPC: G06T1/20 ,  G06T1/60 ,  G06T9/00 ,  H04N19/91

Abstract: A computer vision system is provided that includes a camera capture component configured to capture an image from a camera, a memory, and an image compression decompression engine (ICDE) coupled to the memory and configured to receive each line of the image, and compress each line to generate a compressed bit stream. To compress a line, the ICDE is configured to divide the line into compression units, and compress each compression unit, wherein to compress a compression unit, the ICDE is configured to perform delta prediction on the compression unit to generate a delta predicted compression unit, compress the delta predicted compression unit using exponential Golomb coding to generate a compressed delta predicted compression unit, and add the compressed delta predicted compression unit to the compressed bit stream.

公开(公告)号：US12167049B2

公开(公告)日：2024-12-10

申请号：US18197177

申请日：2023-05-15

Applicant: Texas Instruments Incorporated

Inventor： Ranga Ramanujam Srinivasan ,  Chaitanya Satish Ghone ,  Mihir Narendra Mody ,  Minhua Zhou

IPC: H04N19/895 ,  H04N19/107 ,  H04N19/172 ,  H04N19/39 ,  H04N19/65

Abstract: A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture.

公开(公告)号：US20240370170A1

公开(公告)日：2024-11-07

申请号：US18770866

申请日：2024-07-12

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha ,  Mel Alan Phipps ,  Prasad Jondhale ,  Mohd Asif Farooqui ,  Shailesh Ghotgalkar

IPC: G06F3/06

Abstract: Various examples disclosed herein relate to allocation of code and data of application software among memory of a microcontroller unit (MCU), and more particularly to allocating portions of the application software to random access memory or flash memory of an MCU based on information associated with of each portion of the application software. A method is provided herein that comprises instructing an MCU to execute an application software. The method further comprises obtaining information indicative of a performance of portions of the application software on the MCU and capacity requirements of the portions of the application software, and designating, based on the information, each of the portions of the application software for execution from either a first memory or a second memory when deployed to one or more MCUs.

公开(公告)号：US12050929B2

公开(公告)日：2024-07-30

申请号：US17123653

申请日：2020-12-16

Applicant: Texas Instruments Incorporated

Inventor： Hetul Sanghvi ,  Niraj Nandan ,  Mihir Narendra Mody ,  Kedar Satish Chitnis

IPC: G06F9/48 ,  G06F9/50

CPC classification number: G06F9/4812 ,  G06F9/5027 ,  G06F2209/5018

Abstract: A data processing device is provided that includes a plurality of hardware data processing nodes, wherein each hardware data processing node performs a task, and a hardware thread scheduler including a plurality of hardware task schedulers configured to control execution of a respective task on a respective hardware data processing node of the plurality of hardware data processing nodes, and a proxy hardware task scheduler coupled to a data processing node external to the data processing device, wherein the proxy hardware task scheduler is configured to control execution of a task by the external data processing device, wherein the hardware thread scheduler is configurable to execute a thread of tasks, the tasks including the task controlled by the proxy hardware task scheduler and a first task controlled by a first hardware task scheduler of the plurality of hardware task schedulers.