Switching device and methods for controlling electron tunneling therein
    81.
    发明授权
    Switching device and methods for controlling electron tunneling therein 有权
    用于控制电子隧穿的开关装置和方法

    公开(公告)号:US08502198B2

    公开(公告)日:2013-08-06

    申请号:US11414578

    申请日:2006-04-28

    IPC分类号: H01L29/08

    摘要: A switching device includes at least one bottom electrode and at least one top electrode. The top electrode crosses the bottom electrode at a non-zero angle, thereby forming a junction. A metal oxide layer is established on at least one of the bottom electrode or the top electrode. A molecular layer including a monolayer of organic molecules and a source of water molecules is established in the junction. Upon introduction of a forward bias, the molecular layer facilitates a redox reaction between the electrodes, thereby reducing a tunneling gap between the electrodes.

    摘要翻译: 开关装置包括至少一个底部电极和至少一个顶部电极。 顶部电极以非零角度穿过底部电极,从而形成结。 在底电极或顶电极中的至少一个上建立金属氧化物层。 在连接处建立了包括有机分子单层和水分子源的分子层。 在引入正向偏压时,分子层促进电极之间的氧化还原反应,从而减少电极之间的隧道间隙。

    Mixed-scale electronic interface
    82.
    发明授权
    Mixed-scale electronic interface 有权
    混合电子接口

    公开(公告)号:US07692215B2

    公开(公告)日:2010-04-06

    申请号:US11701086

    申请日:2007-01-31

    IPC分类号: H01L27/10 H01L29/73

    摘要: Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. The predominantly nanoscale layer, in one embodiment of the present invention, comprises a tessellated pattern of submicroscale or microscale pads densely interconnected by nanowire junctions between sets of parallel, closely spaced nanowire bundles. The predominantly submicroscale or microscale layer includes pins positioned complementarily to the submicroscale or microscale pads in the predominantly nanoscale layer. Pins can be configured according to any periodic tiling of the microscale layer.

    摘要翻译: 本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口,其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。 在本发明的一个实施方案中,主要是纳米尺度层包括通过平行的,紧密间隔的纳米线束组之间的纳米线结密合地互连的亚微米级或微米级的镶嵌图案。 主要是亚微米级或微尺度层包括与主要是纳米级层中的亚微米级或微尺度焊盘互补定位的引脚。 引脚可以根据微层的任何周期性平铺进行配置。

    Multilevel imprint lithography
    83.
    发明申请
    Multilevel imprint lithography 失效
    多层压印光刻

    公开(公告)号:US20100112809A1

    公开(公告)日:2010-05-06

    申请号:US11636264

    申请日:2006-12-07

    IPC分类号: H01L21/768

    摘要: A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate.

    摘要翻译: 提供具有突出图案的模具,其通过压印过程被压入薄聚合物膜。 提供了纳米线和微丝之间的控制连接以及电子电路的其它光刻元件。 打印印记被配置成形成大致平行的纳米线的阵列,其具有(1)X方向上的微尺寸,(2)在Y方向上的纳米尺寸和纳米间距,以及Z方向上的三个或更多个不同的高度。 如此形成的印章可以用于将特定的单个纳米线连接到微细线或垫的特定微观区域。 模具中的突出图案在薄聚合物膜中产生凹陷,因此聚合物层获得模具上图案的相反。 在除去模具之后,处理膜,使得聚合物图案可以在基底上的金属/半导体图案上转印。

    Multilevel imprint lithography
    84.
    发明授权
    Multilevel imprint lithography 有权
    多层压印光刻

    公开(公告)号:US07256435B1

    公开(公告)日:2007-08-14

    申请号:US10453329

    申请日:2003-06-02

    IPC分类号: H01L27/10

    摘要: A mold with a protruding pattern is provided that is pressed into a thin polymer film via an imprinting process. Controlled connections between nanowires and microwires and other lithographically-made elements of electronic circuitry are provided. An imprint stamp is configured to form arrays of approximately parallel nanowires which have (1) micro dimensions in the X direction, (2) nano dimensions and nano spacing in the Y direction, and three or more distinct heights in the Z direction. The stamp thus formed can be used to connect specific individual nanowires to specific microscopic regions of microscopic wires or pads. The protruding pattern in the mold creates recesses in the thin polymer film, so the polymer layer acquires the reverse of the pattern on the mold. After the mold is removed, the film is processed such that the polymer pattern can be transferred on a metal/semiconductor pattern on the substrate.

    摘要翻译: 提供具有突出图案的模具,其通过压印过程被压入薄聚合物膜。 提供了纳米线和微丝之间的控制连接以及电子电路的其它光刻元件。 打印印记被配置成形成大致平行的纳米线的阵列,其具有(1)X方向上的微尺寸,(2)在Y方向上的纳米尺寸和纳米间距,以及Z方向上的三个或更多个不同的高度。 如此形成的印章可以用于将特定的单个纳米线连接到微细线或垫的特定微观区域。 模具中的突出图案在薄聚合物膜中产生凹陷,因此聚合物层获得模具上图案的相反。 在除去模具之后,处理膜,使得聚合物图案可以在基底上的金属/半导体图案上转印。

    Three dimensional multilayer circuit
    85.
    发明授权
    Three dimensional multilayer circuit 有权
    三维多层电路

    公开(公告)号:US09324718B2

    公开(公告)日:2016-04-26

    申请号:US13260019

    申请日:2010-01-29

    摘要: A three dimensional multilayer circuit (600) includes a plurality of crossbar arrays (512) made up of intersecting crossbar segments (410, 420) and programmable crosspoint devices (514) interposed between the intersecting crossbar segments (410, 420). Shift pins (505, 510) are used to shift connection domains (430) of the intersecting crossbar segments (410, 420) between stacked crossbar arrays (512) such that the programmable crosspoint devices (514) are uniquely addressed. The shift pins (505, 510) make electrical connections between crossbar arrays (512) by passing vertically between crossbar segments (410, 510) in the first crossbar array (512) and crossbar segments in a second crossbar array. A method for transforming multilayer circuits is also described.

    摘要翻译: 三维多层电路(600)包括由相交的横杆段(410,420)和插入在相交的横杆段(410,420)之间的可编程交叉点装置(514)组成的多个横杆阵列(512)。 移位销(505,510)用于使堆叠的横杆阵列(512)之间的交叉横截面段(410,420)的连接区域(430)移位,使得可编程交叉点设备(514)被唯一地寻址。 换档销(505,510)通过在第一交叉杆阵列(512)中的横杆段(410,510)和第二横杆阵列中的横杆段之间垂直地穿过横杆阵列(512)之间进行电连接。 还描述了用于转换多层电路的方法。

    COMPACT SENSOR SYSTEM
    87.
    发明申请
    COMPACT SENSOR SYSTEM 有权
    紧凑型传感器系统

    公开(公告)号:US20110267610A1

    公开(公告)日:2011-11-03

    申请号:US12772063

    申请日:2010-04-30

    IPC分类号: G01J3/44

    CPC分类号: G01N21/658 G01N21/7746

    摘要: A compact sensor system comprising: an analysis cell configured for photon-matter interaction, where photons are received from a light source; and an integrated-optical spectral analyzer configured for identifying a set of frequencies, the integrated-optical spectral analyzer comprising: a waveguide coupled with the analysis cell, the waveguide configured for propagating a set of frequencies through the waveguide; one or more ring resonators coupled with the waveguide, the one or more ring resonators comprising a predetermined bandwidth and configured for capturing the set of frequencies corresponding to frequencies within the predetermined bandwidth; and one or more frequency detectors coupled with the one or more tunable ring resonators, the one or more frequency detectors configured for generating electrical signals that identify each of the set of frequencies.

    摘要翻译: 一种紧凑的传感器系统,包括:配置用于光子 - 物质相互作用的分析单元,其中从光源接收光子; 所述集成光谱分析仪包括:与所述分析单元耦合的波导,所述波导被配置为通过所述波导传播一组频率;以及波导,其被配置为用于识别一组频率。 一个或多个与所述波导耦合的环形谐振器,所述一个或多个环形谐振器包括预定带宽并被配置用于捕获与所述预定带宽内的频率相对应的频率集合; 以及与所述一个或多个可调环形谐振器耦合的一个或多个频率检测器,所述一个或多个频率检测器被配置用于产生标识所述一组频率中的每一个的电信号。

    Integrated circuits having photonic interconnect layers and methods for fabricating same
    88.
    发明申请
    Integrated circuits having photonic interconnect layers and methods for fabricating same 有权
    具有光互连层的集成电路及其制造方法

    公开(公告)号:US20080246106A1

    公开(公告)日:2008-10-09

    申请号:US11732549

    申请日:2007-04-03

    IPC分类号: H01L31/0232

    摘要: Various embodiments of the present invention are directed to integrated circuits having photonic interconnect layers and methods for fabricating the integrated circuits. In one embodiment of the present invention, an integrated circuit comprises an electronic device layer and one or more photonic interconnect layers. The electronic device layer includes one or more electronic devices, and the electronic device layer is attached to a surface of an intermediate layer. One of the photonic interconnect layers is attached to an opposing surface of the intermediate layer, and each of the photonic interconnect layers has at least one photonic device in communication with at least one of the electronic devices of the electronic device layer.

    摘要翻译: 本发明的各种实施例涉及具有光子互连层的集成电路和用于制造集成电路的方法。 在本发明的一个实施例中,集成电路包括电子器件层和一个或多个光子互连层。 电子器件层包括一个或多个电子器件,并且电子器件层附着到中间层的表面。 光子互连层中的一个附着到中间层的相对表面,并且每个光子互连层具有与电子器件层的至少一个电子器件通信的至少一个光子器件。

    Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays
    89.
    发明申请
    Methods and systems for implementing logic gates with spintronic devices located at nanowire crossbar junctions of crossbar arrays 有权
    用于实现位于横杆阵列的纳米线交叉点处的自旋电子器件的逻辑门的方法和系统

    公开(公告)号:US20080100345A1

    公开(公告)日:2008-05-01

    申请号:US11590959

    申请日:2006-10-31

    IPC分类号: H03K19/20

    摘要: Various method and system embodiments of the present invention are directed to implementing serial logic gates using nanowire-crossbar arrays with spintronic devices located at nanowire-crossbar junctions. In one embodiment of the present invention, a nanowire-crossbar array comprises a first nanowire and a number of substantially parallel control nanowires positioned so that each control nanowire overlaps the first nanowire. The nanowire-crossbar array includes a number of spintronic devices. Each spintronic device is configured to connect one of the control nanowires to the first nanowire and operate as a latch for controlling signal transmissions between the control nanowire and the first nanowire.

    摘要翻译: 本发明的各种方法和系统实施例涉及使用位于纳米线交叉点处的自旋电子器件的纳米线交叉阵列来实现串行逻辑门。 在本发明的一个实施例中,纳米线交叉串阵列包括第一纳米线和多个基本上平行的控制纳米线,所述纳米线被定位成使得每个对照纳米线与第一纳米线重叠。 纳米线交叉开关阵列包括许多自旋电子器件。 每个自旋电子设备被配置为将控制纳米线中的一个连接到第一纳米线并且用作用于控制控制纳米线和第一纳米线之间的信号传输的锁存器。