公开(公告)号：US20090240860A1

公开(公告)日：2009-09-24

申请号：US12054267

申请日：2008-03-24

申请人： Brett W. Coon ,  John R. Nickolls ,  Lars Nyland ,  Peter C. Mills

发明人： Brett W. Coon ,  John R. Nickolls ,  Lars Nyland ,  Peter C. Mills

IPC分类号： G06F12/14

CPC分类号： G06F12/084 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/30185 ,  G06F9/526 ,  G06F2209/521

摘要： A system and method for locking and unlocking access to a shared memory for atomic operations provides immediate feedback indicating whether or not the lock was successful. Read data is returned to the requestor with the lock status. The lock status may be changed concurrently when locking during a read or unlocking during a write. Therefore, it is not necessary to check the lock status as a separate transaction prior to or during a read-modify-write operation. Additionally, a lock or unlock may be explicitly specified for each atomic memory operation. Therefore, lock operations are not performed for operations that do not modify the contents of a memory location.

摘要翻译： 用于锁定和解锁对原子操作的共享存储器的访问的系统和方法提供指示锁是否成功的即时反馈。 读取数据将返回给具有锁定状态的请求者。 在写入期间在读取或解锁期间锁定时，锁定状态可能会同时更改。 因此，在读取 - 修改 - 写入操作之前或期间，不必将锁定状态检查为单独的事务。 另外，可以为每个原子存储器操作明确地指定锁定或解锁。 因此，对于不修改内存位置的内容的操作，不执行锁定操作。

公开(公告)号：US07403964B2

公开(公告)日：2008-07-22

申请号：US10459988

申请日：2003-06-12

申请人： Joshua Porten ,  Won Kim ,  Scott D. Johnson ,  John R. Nickolls

发明人： Joshua Porten ,  Won Kim ,  Scott D. Johnson ,  John R. Nickolls

IPC分类号： G06F15/00 ,  H03M13/00

CPC分类号： G06F7/724

摘要： A Galois field multiplier array includes a 1st register, a 2nd register, a 3rd register, and a plurality of multiplier cells. The 1st register stores bits of a 1st operand. The 2nd register stores bits of a 2nd operand. The 3rd register stores bits of a generating polynomial that corresponds to one of a plurality of applications (e.g., FEC, CRC, Reed Solomon, et cetera). The plurality of multiplier cells is arranged in rows and columns. Each of the multiplier cells outputs a sum and a product and each cell includes five inputs. The 1st input receives a preceding cell's multiply output, the 2nd input receives at least one bit of the 2nd operand, the 3rd input receives a preceding cell's sum output, a 4th input receives at least one bit of the generating polynomial, and the 5th input receives a feedback term from a preceding cell in a preceding row. The multiplier cells in the 1st row have the 1st input, 3rd input, and 5th input set to corresponding initialization values in accordance with the 2nd operand.

摘要翻译： 伽罗瓦域倍增器阵列包括1 寄存器，第二寄存器，第三寄存器和多个乘法器单元。 1＆lt; ST＆gt;寄存器存储1＆lt; ST＆gt;操作数的位。 2 寄存器存储第2个操作数的位。 3 寄存器存储对应于多个应用中的一个应用（例如，FEC，CRC，Reed Solomon等）的生成多项式的比特。 多个乘法器单元被排列成行和列。 每个乘法器单元输出和和乘积，并且每个单元包括五个输入。 1 ^{输入接收前一个单元的乘法输出，第二个输入端接收第二个操作数的至少一位，3个< SUP> rd 输入接收前一个单元的和输出，第4个输入接收生成多项式的至少一个位，并且第5个输入接收一个 来自前一行中的前一个单元格的反馈项。 1 行中的乘法器单元具有1 输入，3 输入和5 输入 根据第2操作数设置为相应的初始化值。}

公开(公告)号：US07343472B2

公开(公告)日：2008-03-11

申请号：US10459907

申请日：2003-06-11

申请人： Joshua Porten ,  Won Kim ,  Scott D. Johnson ,  John R. Nickolls

发明人： Joshua Porten ,  Won Kim ,  Scott D. Johnson ,  John R. Nickolls

IPC分类号： G06F15/76 ,  G06F9/30 ,  G06F9/40 ,  G06F7/00 ,  G06F15/00 ,  G06F7/38 ,  G06F9/00 ,  G06F9/44 ,  H03M13/00

CPC分类号： G06F7/724 ,  G06F9/30018

摘要： A processor includes an instruction memory, arithmetic logic unit, finite field arithmetic unit, at least one digital storage device, and an instruction decoder. The instruction memory temporarily stores an instruction that includes at least one of: an operational code, destination information, and source information. The instruction decoder is operably coupled to interpret the instruction to identify the arithmetic logic unit and/or the finite field arithmetic unit to perform the operational code of the corresponding instruction. The instruction decoder then identifies at least one destination location within the digital storage device based on the destination information contained within the corresponding instruction. The instruction decoder then identifies at least one source location within the digital storage device based on the source information of the corresponding instruction. When the finite field arithmetic unit is to perform the operational code, it performs a finite field arithmetic function upon data stored in the at least one source location in accordance with the operational code and provides the resultant to the destination location.

摘要翻译： 处理器包括指令存储器，算术逻辑单元，有限域算术单元，至少一个数字存储设备和指令解码器。 指令存储器临时存储包括以下操作代码，目的地信息和源信息中的至少一个的指令。 指令解码器可操作地耦合以解释用于识别算术逻辑单元和/或有限域运算单元的指令以执行相应指令的操作代码。 然后，指令解码器基于包含在相应指令内的目的地信息来识别数字存储设备内的至少一个目的地位置。 然后，指令解码器基于相应指令的源信息识别数字存储设备内的至少一个源位置。 当有限域算术单元要执行操作代码时，它根据操作代码对存储在至少一个源位置的数据执行有限域算术功能，并将结果提供给目的地位置。