公开(公告)号：US08560906B2

公开(公告)日：2013-10-15

申请号：US13285899

申请日：2011-10-31

申请人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

发明人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G01R31/318328 ,  G01R31/3177 ,  G01R31/31835 ,  G01R31/318357 ,  G06F17/5009

摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

公开(公告)号：US20120174049A1

公开(公告)日：2012-07-05

申请号：US13285899

申请日：2011-10-31

申请人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

发明人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

IPC分类号： G06F17/50

CPC分类号： G01R31/318328 ,  G01R31/3177 ,  G01R31/31835 ,  G01R31/318357 ,  G06F17/5009

摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

摘要翻译： 这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。 在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。 定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。 为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。 实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

公开(公告)号：US20070288822A1

公开(公告)日：2007-12-13

申请号：US11796374

申请日：2007-04-27

申请人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

发明人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

IPC分类号： G06F9/455 ,  G01R31/3183

CPC分类号： G01R31/318328 ,  G01R31/3177 ,  G01R31/31835 ,  G01R31/318357 ,  G06F17/5009

摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

摘要翻译： 这里公开了用于执行定时感知自动测试模式生成（ATPG）的示例性方法，装置和系统，其可以用于例如为了提高用于检测延迟缺陷或保持时间缺陷而产生的测试集的质量。 在某些实施例中，从各种源（例如，从标准延迟格式（SDF）文件）导出的定时信息被集成到ATPG工具中。 定时信息可用于引导测试发生器通过某些路径（例如，具有选定长度的路径或长度范围，例如最长或最短路径）来检测故障。 为了避免重复通过类似路径传播故障，可以使用加权随机方法来提高测试生成过程中的路径覆盖。 实验结果表明，当将工业设计应用于定时识别ATPG的实施例时，可以实现显着的测试质量改进。

公开(公告)号：US20180045780A1

公开(公告)日：2018-02-15

申请号：US15664169

申请日：2017-07-31

申请人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

发明人： Xijiang Lin ,  Kun-Han Tsai ,  Mark Kassab ,  Chen Wang ,  Janusz Rajski

IPC分类号： G01R31/3183 ,  G01R31/3177 ,  G06F17/50

CPC分类号： G01R31/318328 ,  G01R31/3177 ,  G01R31/31835 ,  G01R31/318357 ,  G06F17/5009

摘要： Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.

公开(公告)号：US20150285854A1

公开(公告)日：2015-10-08

申请号：US13635683

申请日：2011-03-16

申请人： Mark A. Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Jakub Janicki ,  Tyszer Jerzy

发明人： Mark A. Kassab ,  Grzegorz Mrugalski ,  Nilanjan Mukherjee ,  Janusz Rajski ,  Jakub Janicki ,  Tyszer Jerzy

IPC分类号： G01R31/28

CPC分类号： G01R31/2834 ,  G01R31/2851 ,  G01R31/318335 ,  G01R31/318547 ,  G01R31/31921

摘要： Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.

摘要翻译： 公开了测试压缩环境中用于测试调度和测试访问的方法，装置和系统的代表性实施例。 基于包括压缩测试数据，对应的测试仪通道要求和相关核心的测试信息形成用于测试电路中的多个核心的测试模式的集群。 测试模式集群的形成之后是测试者信道分配。 可以采用最佳拟合方案或平衡拟合方案来产生信道分配信息。 可以基于信道分配信息来设计用于动态信道分配的测试接入电路。

公开(公告)号：US08356222B2

公开(公告)日：2013-01-15

申请号：US12718822

申请日：2010-03-05

申请人： Nilanjan Mukherjee ,  Artur Pogiel ,  Janusz Rajski ,  Jerzy Tyszer

发明人： Nilanjan Mukherjee ,  Artur Pogiel ,  Janusz Rajski ,  Jerzy Tyszer

IPC分类号： G01R31/28

CPC分类号： G11C29/40 ,  G11C16/04 ,  G11C17/14 ,  G11C29/20 ,  G11C29/56 ,  G11C29/56008 ,  G11C2029/0401 ,  G11C2029/1208 ,  G11C2029/5606

摘要： Fault diagnosis techniques for non-volatile memories are disclosed. The techniques are based on deterministic partitioning of rows and/or columns of cells in a memory array. Through deterministic partitioning, signatures are generated for identification of failing rows, columns and single memory cells. A row/column selector or a combined row and column selector may be built on chip to implement the process of deterministic partitioning. An optional shadow register may be used to transfer obtained signatures to an automated test equipment (ATE).

摘要翻译： 公开了用于非易失性存储器的故障诊断技术。 这些技术基于对存储器阵列中的单元格行和/或列的确定性划分。 通过确定性分区，生成签名以识别失败的行，列和单个存储单元。 行/列选择器或组合的行和列选择器可以构建在芯片上以实现确定性分区的过程。 可以使用可选的影子寄存器将获得的签名转移到自动测试设备（ATE）。

公开(公告)号：US07653851B2

公开(公告)日：2010-01-26

申请号：US12412267

申请日：2009-03-26

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/28

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

摘要翻译： 公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

公开(公告)号：US20100083063A1

公开(公告)日：2010-04-01

申请号：US12633601

申请日：2009-12-08

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

摘要翻译： 公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

公开(公告)号：US20090187800A1

公开(公告)日：2009-07-23

申请号：US12412267

申请日：2009-03-26

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters—circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

摘要翻译： 公开了用于自动合成移相器的方法，该移相器用于消除驱动并行扫描链的伪随机测试图形发生器所特征的结构依赖性的影响。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。

公开(公告)号：US20070300110A1

公开(公告)日：2007-12-27

申请号：US11895845

申请日：2007-08-27

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Nagesh Tamarapalli

IPC分类号： G01R31/3183 ,  G06F11/26

CPC分类号： G01R31/318541 ,  G01R31/31813 ,  G01R31/318385 ,  G01R31/318547 ,  G01R31/318594

摘要： A method is disclosed for the automated synthesis of phase shifters. Phase shifters comprise circuits used to remove effects of structural dependencies featured by pseudo-random test pattern generators driving parallel scan chains. Using a concept of duality, the method relates the logical states of linear feedback shift registers (LFSRs) and circuits spacing their inputs to each of the output channels. The method generates a phase shifter network balancing the loads of successive stages of LFSRs and satisfying criteria of reduced linear dependency, channel separation and circuit complexity.

摘要翻译： 公开了用于自动合成移相器的方法。 移相器包括用于消除驱动并行扫描链的伪随机测试图形发生器特征的结构依赖性的影响的电路。 使用二元性概念，该方法涉及线性反馈移位寄存器（LFSR）的逻辑状态和将输入间隔到每个输出通道的电路。 该方法产生平衡LFSR的连续级的负载的移相器网络，并且满足减少的线性依赖性，信道分离和电路复杂度的标准。