公开(公告)号：US20210151602A1

公开(公告)日：2021-05-20

申请号：US17248520

申请日：2021-01-28

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei ZHOU

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/02 ,  H01L21/324 ,  H01L21/768 ,  H01L21/265 ,  H01L29/10

摘要： A semiconductor structure is provided. The semiconductor structure includes a gate structure on a base substrate; a first stress layer in the base substrate on both sides of the gate structure; and a second stress layer in the first stress layer and surrounded by the first stress layer. The doping concentration of the second stress layer is greater than or equal to a doping concentration of the first stress layer.

公开(公告)号：US11011412B2

公开(公告)日：2021-05-18

申请号：US16556743

申请日：2019-08-30

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Wei Shi ,  Youcun Hu ,  Xiamei Tang

IPC分类号： H01L23/58 ,  H01L21/768 ,  H01L21/033 ,  H01L21/311 ,  H01L21/02

摘要： A semiconductor structure and a method for forming same are provided. In one form, a forming method includes: providing a base, where a core layer is formed on the base, a hard mask layer is formed on the core layer, and a first mask opening is formed in the hard mask layer; forming a first mask trench in the core layer exposed from the first mask opening, the first mask trench including a plurality of mask sub-trenches along an extending direction, where the mask sub-trenches are isolated from each other using the core layer exposed from the first mask opening; forming a first spacer on a side wall of the mask sub-trench; removing a core layer of a region in which the first mask opening is located, and forming, at a position corresponding to the core layer, a second mask trench enclosed by the first spacer and the base, the second mask trench and the first mask trench being isolated from each other using the first spacer; and forming a second spacer on a side wall of the second mask trench, where both the first spacer and the base, and the second spacer and the base, enclose a first target trench. The first spacer and the second spacer whose side walls contact with each other are used as a cutting member, alleviating rounding of a head of the first target trench.

公开(公告)号：US11011410B2

公开(公告)日：2021-05-18

申请号：US16282126

申请日：2019-02-21

申请人： SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION ,  NINGBO SEMICONDUCTOR INTERNATIONAL CORPORATION

发明人： Ji Guang Zhu ,  Hai Ting Li

IPC分类号： H01L21/762 ,  H01L27/12 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/8258 ,  H01L21/84

摘要： A method for forming a semiconductor device includes forming a first insulator layer on a first substrate of a first semiconductor material, implanting hydrogen ions into the first substrate to form a hydrogen-implanted layer, forming a recessed region in the first substrate, forming a second semiconductor material in the recessed region, and forming a second insulator layer over the second semiconductor material and the first substrate. The method also includes providing a second substrate with a third insulator layer disposed thereon, bonding the first substrate with the second substrate, and removing a lower portion of the first substrate at the hydrogen-implanted layer. A portion of the first substrate is removed to expose a surface of the second semiconductor material in the recessed region, thereby providing a layer of the first semiconductor material adjacent to a layer of the second semiconductor material on the second insulator layer.

公开(公告)号：US20210125876A1

公开(公告)日：2021-04-29

申请号：US17247984

申请日：2021-01-04

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  SMIC New Technology Research and Development (Shanghai) Corporation

发明人： Fei ZHOU

IPC分类号： H01L21/8238 ,  H01L21/762 ,  H01L29/66 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/8234

摘要： A semiconductor device is provided. The semiconductor device includes a semiconductor substrate; fins on the semiconductor substrate; an isolation layer formed on the semiconductor substrate and between adjacent fins; and gate structures on sides of the isolation layer. The isolation layer has a top surface higher than top surfaces of the fins and passes through the fins along a direction perpendicular to an extending direction of the fins and in parallel with a surface of the semiconductor substrate.

公开(公告)号：US10991794B2

公开(公告)日：2021-04-27

申请号：US16181786

申请日：2018-11-06

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Poren Tang

IPC分类号： H01L29/06 ,  H01L29/66 ,  H01L29/417 ,  H01L21/768 ,  H01L29/49 ,  H01L29/78 ,  H01L21/764

摘要： The present specification discloses a semiconductor device and a method for manufacturing same. In one implementation, the method may include: providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a gate structure disposed on the substrate, initial spacer layers on side surfaces of two sides of the gate structure, and a first inter-layer dielectric layer covering the gate structure and the initial spacer layers; and the substrate includes a source and a drain respectively located on the two sides of the gate structure; etching the first inter-layer dielectric layer to form a source contact hole and a drain contact hole that expose a part of the initial spacer layer; removing the exposed part of the initial spacer layer to expose the side surface of the gate structure; forming a spacer structure layer on the exposed side surface of the gate structure; forming a source contact member and a drain contact member in the contact holes; selectively removing at least a part of the spacer structure layer to form an air gap; and forming a second inter-layer dielectric layer covering the air gap. In the present invention, an air gap spacer structure can be formed and parasitic capacitance is reduced.

公开(公告)号：US10991690B2

公开(公告)日：2021-04-27

申请号：US16424924

申请日：2019-05-29

申请人： Semiconductor Manufacturing International (Beijing) Corporation ,  Semiconductor Manufacturing International (Shanghai) Corporation

发明人： Nan Wang

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/02 ,  H01L29/161 ,  H01L21/3065 ,  H01L29/78 ,  H01L21/8234 ,  H01L29/06

摘要： A semiconductor structure and a method for forming same are provided. The forming method includes: providing a substrate, a fin protruding from the substrate, and at least two channel laminates sequentially located on the fin, where each channel laminate includes a sacrificial layer and a channel layer; forming a gate structure across the channel laminates; forming, in the channel laminates, a groove that exposes the fin, where after the groove is formed, the fin, the channel layer adjacent to the fin, and the remaining sacrificial layer encircle a first trench, adjacent channel layers and the remaining sacrificial layer between the adjacent channel layers encircle a second trench; forming first spacers in the first trench and the second trench; and forming a source-drain doping layer in the groove.

公开(公告)号：US10991596B2

公开(公告)日：2021-04-27

申请号：US16537100

申请日：2019-08-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Jin Jisong

IPC分类号： H01L21/311 ,  H01L21/033 ,  H01L21/027 ,  H01L21/308 ,  H01L21/3213

摘要： A semiconductor structure and a method for forming the same are provided. The forming method may include: providing a base; forming, on the base, a to-be-etched material layer, a core material layer located on the to-be-etched material layer, and an HM material layer located on the core material layer; patterning the HM material layer to form HM layers; etching the core material layer between adjacent HM layers, forming a plurality of first grooves exposed from the to-be-etched material layer, and using the remaining core material layer as a core layer; and forming a side wall layer on side walls of the first groove and the HM layer; after the side wall layer is formed, removing the HM layer and the core layer at the bottom of the HM layer, and forming a plurality of second grooves exposed from the to-be-etched material layer; and removing the to-be-etched material layer at the bottom of the first groove and the second groove by using the side wall layer and the remaining core layer as masks, to form a target pattern. In embodiments and implementations of the present disclosure, the pattern precision of the first groove and the second groove is improved. After the target pattern is formed, the pattern precision of the target pattern is correspondingly improved.

公开(公告)号：US10983160B2

公开(公告)日：2021-04-20

申请号：US16002858

申请日：2018-06-07

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Chia Chi Yang ,  Zhi Bing Deng ,  Teng Ye Wang ,  Wen Jun Weng

IPC分类号： G01R31/30 ,  G01R19/15 ,  G01R19/155 ,  G01R19/00 ,  G01R27/26

摘要： Circuits and methods for measuring a working current of a circuit module. An exemplary circuit for measuring a working current of a circuit module includes a capacitor. The capacitor supplies a voltage to the circuit module using a voltage on the two terminals of the capacitor. The circuit also includes a voltage measuring module. The voltage measuring module measures a voltage change amount on the two terminals of the capacitor in an unit time. The working current of the circuit module is determined by the circuit according to the voltage change amount on the two terminals of the capacitor in the unit time and a capacitance of the capacitor.

公开(公告)号：US10978575B2

公开(公告)日：2021-04-13

申请号：US16596953

申请日：2019-10-09

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Hao Deng

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L21/768 ,  H01L21/02 ,  H01L29/51 ,  H01L29/49 ,  H01L21/28

摘要： A semiconductor structure is provided and includes a substrate; a gate dielectric layer on the substrate; a dielectric barrier layer structure on the gate dielectric layer; a work function layer on the dielectric barrier layer structure; a gate barrier layer structure on the work function layer; and a gate electrode layer on the gate barrier layer structure. The dielectric barrier layer structure is doped with silicon and the gate barrier layer structure is doped with silicon.

公开(公告)号：US10971405B2

公开(公告)日：2021-04-06

申请号：US16419416

申请日：2019-05-22

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Nan Wang

IPC分类号： H01L21/8238 ,  H01L21/28 ,  H01L21/266 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78 ,  H01L21/033

摘要： A method for fabricating a semiconductor device includes providing a base substrate, including a first region and a second region. The first region is located on each side of the second region, and a plurality of fin structures is formed in the first region and the second region. The method includes forming a first doped region and a second doped region in the first region and the second region, respectively in the plurality of fin structures. The concentration of doping ions in the first doped region is lower than that in the second doped region, and the doping ions in the first doped region and the second doped region are the same doping type. After forming the first doped region and the second doped region, the method includes forming a plurality of gate structures on the first doped region and the second doped region across the plurality of fin structures.