公开(公告)号：US08762808B2

公开(公告)日：2014-06-24

申请号：US13402088

申请日：2012-02-22

申请人： Moshe Bukris ,  Shai Kalfon ,  Yair Amitay

发明人： Moshe Bukris ,  Shai Kalfon ,  Yair Amitay

IPC分类号： H03M13/00

CPC分类号： G06F11/1048 ,  H03M13/2739 ,  H03M13/2775 ,  H03M13/2978 ,  H03M13/3972 ,  H03M13/6525 ,  H03M13/6561 ,  H03M13/6566

摘要： An apparatus comprising a decoder circuit and a memory. The decoder circuit may be configured to generate a single address signal to read a first parity data signal, a second parity data signal and read and/or write systematic information data, a first a-priori-information signal and a second a-priori-information signal. The decoder circuit (i) reads the first parity data signal, the systematic information data and the first a-priori-information during even half-iterations of a decoding operation and (ii) reads the second parity data, the systematic information data and the second a-priori-information during odd half-iterations of the decoding operation. The memory may be configured to store the systematic information data and the first and second a-priori-information signals such that each are accessible by the single address signal.

摘要翻译： 一种包括解码器电路和存储器的装置。 解码器电路可以被配置为产生单个地址信号以读取第一奇偶校验数据信号，第二奇偶校验数据信号和读取和/或写入系统信息数据，第一先验信息信号和第二先验信息信号， 信息信号。 解码器电路（i）在解码操作的偶数半迭代期间读取第一奇偶校验数据信号，系统信息数据和第一先验信息，以及（ii）读取第二奇偶校验数据，系统信息数据和 第二先验信息在解码操作的奇数半迭代期间。 存储器可以被配置为存储系统信息数据和第一和第二先验信息信号，使得每个可以由单个地址信号访问。

公开(公告)号：US08542752B2

公开(公告)日：2013-09-24

申请号：US13169289

申请日：2011-06-27

申请人： Alexei Gorokhov ,  Avneesh Agrawal ,  Arvind Vijay Keerthi

发明人： Alexei Gorokhov ,  Avneesh Agrawal ,  Arvind Vijay Keerthi

IPC分类号： H04B14/04

CPC分类号： H03M13/2945 ,  H03M13/2903 ,  H03M13/2948 ,  H03M13/2978 ,  H03M13/6362 ,  H03M13/6513 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0065 ,  H04L1/007 ,  H04L5/023 ,  H04L2001/0093 ,  H04N21/2381 ,  H04N21/2383 ,  H04N21/2402 ,  H04N21/2404 ,  H04N21/2405 ,  H04N21/6405 ,  H04N21/6408

摘要： Techniques for sending signaling information using hierarchical coding are described. With hierarchical coding, individual messages for users are encoded using multiple interconnected encoders such that (1) the message for each user is sent at a data rate suitable for that user and (2) a single multicast message is generated for the messages for all users. A base station determines data rates supported by the users and the code rates to achieve these data rates. Each data rate is determined by one or more code rates. Signaling information for the users is mapped to data blocks to be sent at different data rates. Each data block is then encoded in accordance with the code rate(s) associated with the data rate for that data block. A final coded block is generated for all users and transmitted. Each user performs the complementary decoding to recover the message sent to that user.

摘要翻译： 描述使用分层编码发送信令信息的技术。 使用分层编码，使用多个互连的编码器对用户的各个消息进行编码，使得（1）以适合于该用户的数据速率发送每个用户的消息，以及（2）为所有用户生成消息的单个多播消息 。 基站确定用户支持的数据速率和码率来实现这些数据速率。 每个数据速率由一个或多个码率决定。 将用户的信令信息映射到以不同数据速率发送的数据块。 然后根据与该数据块的数据速率相关联的码率对每个数据块进行编码。 为所有用户生成最终编码块并进行传输。 每个用户执行补充解码以恢复发送给该用户的消息。

公开(公告)号：US20130219242A1

公开(公告)日：2013-08-22

申请号：US13402088

申请日：2012-02-22

申请人： Moshe Bukris ,  Shai Kalfon ,  Yair Amitay

发明人： Moshe Bukris ,  Shai Kalfon ,  Yair Amitay

IPC分类号： H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1048 ,  H03M13/2739 ,  H03M13/2775 ,  H03M13/2978 ,  H03M13/3972 ,  H03M13/6525 ,  H03M13/6561 ,  H03M13/6566

摘要： An apparatus comprising a decoder circuit and a memory. The decoder circuit may be configured to generate a single address signal to read a first parity data signal, a second parity data signal and read and/or write systematic information data, a first a-priori-information signal and a second a-priori-information signal. The decoder circuit (i) reads the first parity data signal, the systematic information data and the first a-priori-information during even half-iterations of a decoding operation and (ii) reads the second parity data, the systematic information data and the second a-priori-information during odd half-iterations of the decoding operation. The memory may be configured to store the systematic information data and the first and second a-priori-information signals such that each are accessible by the single address signal.

摘要翻译： 一种包括解码器电路和存储器的装置。 解码器电路可以被配置为产生单个地址信号以读取第一奇偶校验数据信号，第二奇偶校验数据信号和读取和/或写入系统信息数据，第一先验信息信号和第二先验信息信号， 信息信号。 解码器电路（i）在解码操作的偶数半迭代期间读取第一奇偶校验数据信号，系统信息数据和第一先验信息，以及（ii）读取第二奇偶校验数据，系统信息数据和 第二先验信息在解码操作的奇数半迭代期间。 存储器可以被配置为存储系统信息数据和第一和第二先验信息信号，使得每个可以由单个地址信号访问。

公开(公告)号：US08448033B2

公开(公告)日：2013-05-21

申请号：US12955709

申请日：2010-11-29

申请人： Cheng-Chi Wong ,  Hsi-Chia Chang

发明人： Cheng-Chi Wong ,  Hsi-Chia Chang

IPC分类号： G06F11/00

CPC分类号： H03M13/2775 ,  H03M13/2739 ,  H03M13/2753 ,  H03M13/2771 ,  H03M13/2957 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3972

摘要： An error correction code encoder is provided. A first encoder encodes input information bits and generates first parity check bits. An interleaver interleaves the input information bits and generates permuted information bits. A second encoder encodes the permuted information bits and generates second parity check bits. The interleaver interleaves the input information bits in a window-wise manner so that the input information bits are divided into input information bit windows before being interleaved, and permuted information bit windows having the permuted information bits are generated thereafter. When the input information bit windows are grouped into groups according to different window index characteristics, the window index of each permuted information bit window has the same characteristic as the corresponding input information bit window interleaved therefrom.

摘要翻译： 提供纠错码编码器。 第一编码器对输入信息比特进行编码并产生第一奇偶校验位。 交织器对输入信息比特进行交织并产生置换的信息比特。 第二编码器对置换的信息位进行编码，并产生第二奇偶校验位。 交织器以窗口方式对输入信息比特进行交织，使得输入信息比特在被交织之前被划分为输入信息比特窗口，此后产生具有置换信息比特的置换信息比特窗口。 当输入信息比特窗口根据不同窗口索引特性被分组成组时，每个置换的信息比特窗口的窗口索引具有与其交错的对应的输入信息比特窗口的特征相同的特征。

公开(公告)号：US20120257687A1

公开(公告)日：2012-10-11

申请号：US13169289

申请日：2011-06-27

申请人： Alexei Gorokhov ,  Avneesh Agrawal ,  Arvind Vijay Keerthi

发明人： Alexei Gorokhov ,  Avneesh Agrawal ,  Arvind Vijay Keerthi

IPC分类号： H04L27/00

CPC分类号： H03M13/2945 ,  H03M13/2903 ,  H03M13/2948 ,  H03M13/2978 ,  H03M13/6362 ,  H03M13/6513 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/0065 ,  H04L1/007 ,  H04L5/023 ,  H04L2001/0093 ,  H04N21/2381 ,  H04N21/2383 ,  H04N21/2402 ,  H04N21/2404 ,  H04N21/2405 ,  H04N21/6405 ,  H04N21/6408

摘要： Techniques for sending signaling information using hierarchical coding are described. With hierarchical coding, individual messages for users are encoded using multiple interconnected encoders such that (1) the message for each user is sent at a data rate suitable for that user and (2) a single multicast message is generated for the messages for all users. A base station determines data rates supported by the users and the code rates to achieve these data rates. Each data rate is determined by one or more code rates. Signaling information for the users is mapped to data blocks to be sent at different data rates. Each data block is then encoded in accordance with the code rate(s) associated with the data rate for that data block. A final coded block is generated for all users and transmitted. Each user performs the complementary decoding to recover the message sent to that user.

摘要翻译： 描述使用分层编码发送信令信息的技术。 使用分层编码，使用多个互连的编码器对用户的各个消息进行编码，使得（1）以适合于该用户的数据速率发送每个用户的消息，以及（2）为所有用户生成消息的单个多播消息 。 基站确定用户支持的数据速率和码率来实现这些数据速率。 每个数据速率由一个或多个码率决定。 将用户的信令信息映射到以不同数据速率发送的数据块。 然后根据与该数据块的数据速率相关联的码率对每个数据块进行编码。 为所有用户生成最终编码块并进行传输。 每个用户执行补充解码以恢复发送给该用户的消息。

公开(公告)号：US08276037B2

公开(公告)日：2012-09-25

申请号：US12306637

申请日：2007-06-14

申请人： Andrea Ancora ,  Giuseppe Montalbano

发明人： Andrea Ancora ,  Giuseppe Montalbano

IPC分类号： H03M13/00

CPC分类号： H03M13/29 ,  H03M13/2978 ,  H03M13/45

摘要： The invention related to a turbo decoder comprising SISO decoding modules each other interconnected in a feedback control scheme having scaling modules for applying a scaling factor to extrinsic information delivered by said SISO decoding modules. The turbo decoder comprises a selection module for adaptively selecting said scaling factor based on a number of decoding iterations of the turbo decoder.

摘要翻译： 本发明涉及一种包括SISO解码模块的turbo解码模块，其在具有缩放模块的反馈控制方案中相互连接，该缩放模块用于将缩放因子应用于由所述SISO解码模块传送的外部信息。 turbo解码器包括一个选择模块，用于根据turbo解码器的解码迭代次数自适应地选择所述缩放因子。

公开(公告)号：US20100287437A1

公开(公告)日：2010-11-11

申请号：US12223109

申请日：2007-01-18

申请人： Jean-Baptiste Dore ,  Marie-Hélène Hamon ,  Pierre Penard

发明人： Jean-Baptiste Dore ,  Marie-Hélène Hamon ,  Pierre Penard

IPC分类号： H03M13/27 ,  G06F11/10

CPC分类号： H03M13/2972 ,  H03M13/1194 ,  H03M13/2771 ,  H03M13/2978 ,  H03M13/6566

摘要： A method of low latency encoding of an input bit sequence (S0) to yield an encoded bit sequence (S), and a corresponding decoding method, said encoding method including: a first encoding step (E1) applied to bits of the input bit sequence (S0), using a first code; an interleaving step (E3) in which an interleaver interleaves the bits obtained from said first code; and a parity, second encoding step (E4) applied to the bits obtained from said interleaver, using a second code, to generate said encoded bit sequence (S). The parity, second encoding step (E4) starts after a predetermined number Δ of bits have been interleaved, said predetermined number Δ of bits ranging between a first lower number Δi of bits depending on one or more parameters of said interleaving step (E3) and a first higher number Δs of bits corresponding to the total number of bits to be processed during said interleaving step (E3).

摘要翻译： 一种输入比特序列（S0）的低延迟编码以产生编码比特序列（S）的方法和相应的解码方法，所述编码方法包括：第一编码步骤（E1），其应用于输入比特序列 （S0），使用第一代码; 交织步骤（E3），其中交织器交织从所述第一码获得的比特; 以及使用第二代码应用于从所述交织器获得的比特的奇偶校验第二编码步骤（E4），以生成所述编码比特序列（S）。 奇偶校验第二编码步骤（E4）在预定数量＆Dgr之后开始; 的位已被交织，所述预定数量＆Dgr; 根据所述交织步骤（E3）的一个或多个参数和与在所述交织步骤期间要处理的总位数相对应的比特的第一较高数目＆Dgr比特，位于第一较低数字＆amp; （E3）。

公开(公告)号：US07584409B2

公开(公告)日：2009-09-01

申请号：US11485310

申请日：2006-07-13

申请人： Masao Orio

发明人： Masao Orio

IPC分类号： H03M13/03

CPC分类号： H03M13/2975 ,  H03M13/2978

摘要： A decoding device according to the one embodiment of the invention includes: a first decoder performing a first decoding based on first encoded data obtained by encoding unencoded data, and second soft-output data to generate first soft-output data; a second decoder performing a second decoding based on second encoded data obtained by interleaving the unencoded data and encoding the interleaved data, and the first soft-output data to generate the second soft-output data; and a hard decision part outputting decoded data through hard decision on the first soft-output data.

摘要翻译： 根据本发明的一个实施例的解码装置包括：第一解码器，其基于通过对未编码数据进行编码获得的第一编码数据和第二软输出数据执行第一解码，以产生第一软输出数据; 第二解码器，基于通过对未编码数据进行交织而获得的第二编码数据和对交织数据进行编码，以及第一软输出数据，以产生第二软输出数据; 以及通过对第一软输出数据进行硬判断来输出解码数据的硬决定部。

公开(公告)号：US07570700B2

公开(公告)日：2009-08-04

申请号：US10897200

申请日：2004-07-22

申请人： Kelly B. Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Christopher R. Jones

发明人： Kelly B. Cameron ,  Hau Thien Tran ,  Ba-Zhong Shen ,  Christopher R. Jones

IPC分类号： H04L5/12 ,  H04L23/02

CPC分类号： H03M13/3972 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/25 ,  H03M13/258 ,  H03M13/27 ,  H03M13/2757 ,  H03M13/29 ,  H03M13/2966 ,  H03M13/2978 ,  H03M13/3905 ,  H03M13/3922 ,  H03M13/3927 ,  H03M13/3988 ,  H03M13/4107 ,  H03M13/6505 ,  H03M13/6561 ,  H04L1/0041 ,  H04L1/005 ,  H04L1/006 ,  H04L1/0065 ,  H04L1/0066 ,  H04L1/0068 ,  H04L1/0071

摘要： A method for parallel concatenated (Turbo) encoding and decoding. Turbo encoders receive a sequence of input data tuples and encode them. The input sequence may correspond to a sequence of an original data source, or to an already coded data sequence such as provided by a Reed-Solomon encoder. A turbo encoder generally comprises two or more encoders separated by one or more interleavers. The input data tuples may be interleaved using a modulo scheme in which the interleaving is according to some method (such as block or random interleaving) with the added stipulation that the input tuples may be interleaved only to interleaved positions having the same modulo−N (where N is an integer) as they have in the input data sequence. If all the input tuples are encoded by all encoders then output tuples can be chosen sequentially from the encoders and no tuples will be missed. If the input tuples comprise multiple bits, the bits may be interleaved independently to interleaved positions having the same modulo−N and the same bit position. This may improve the robustness of the code. A first encoder may have no interleaver or all encoders may have interleavers, whether the input tuple bits are interleaved independently or not. Modulo type interleaving also allows decoding in parallel.

公开(公告)号：US20090158130A1

公开(公告)日：2009-06-18

申请号：US12065718

申请日：2006-09-05

申请人： Kyung whoon Cheun ,  Yong sang Kim ,  Wang rok Oh

发明人： Kyung whoon Cheun ,  Yong sang Kim ,  Wang rok Oh

IPC分类号： H03M13/23 ,  G06F11/08 ,  H03M13/27

CPC分类号： H03M13/2978 ,  H03M13/6561

摘要： A method and apparatus for turbo encoding and method and apparatus for turbo decoding are disclosed, by which encoding and decoding speeds of turbo codes and performance thereof can be enhanced. In performing turbo encoding on inputted information bits by a unit of an information frame including a predetermined number of bits, the present invention includes dividing the information frame into at least two information sub-blocks, encoding each of the at least two information sub-blocks independently, rearranging information bits configuring the information frame by interleaving the information frame, dividing the rearranged information frame into at least two information sub-blocks, and encoding each of the at least two information sub-blocks independently.

摘要翻译： 公开了用于turbo编码的方法和装置以及用于turbo解码的方法和装置，通过该方法和装置可以增强turbo码的编码和解码速度及其性能。 本发明的目的在于，对于输入的信息比特进行包含预定比特数的信息帧的Turbo编码，本发明包括将信息帧划分为至少两个信息子块，对至少两个信息子块 独立地通过交织信息帧来重新布置配置信息帧的信息位，将重新排列的信息帧划分为至少两个信息子块，以及独立地编码至少两个信息子块中的每一个。