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    Benes fabric for bit level permutations
    81.
    发明申请
    Benes fabric for bit level permutations 审中-公开
    Benes织物用于位电平排列

    公开(公告)号：US20020150238A1

    公开(公告)日：2002-10-17

    申请号：US09784893

    申请日：2001-02-15

    Inventor： Mark Peting ,  Thad McCracken

    IPC: H04L009/00

    CPC classification number: H04L9/34 ,  H04L9/0618

    Abstract: Methods and apparatuses for bit-level permutations using a Benes fabric are described. In one embodiment, the Benes fabric includes an interconnection of multiple 2null2 switches. The 2null2 switches can be in either a pass-through state or a cross-over state. Each switch is coupled to a control circuit or a control register to control the state of the switch. The manner in which the 2null2 switches are interconnected allows a variety of bit permutations to be selected. The bit permutations can be used, for example, for encryption or decryption of digital data.

    Abstract translation: 描述了使用Benes织物的位级排列的方法和装置。 在一个实施例中，Benes织物包括多个2x2开关的互连。 2x2开关可以处于通过状态或交叉状态。 每个开关耦合到控制电路或控制寄存器以控制开关的状态。 2x2开关互连的方式允许选择各种位排列。 比特排列可用于例如数字数据的加密或解密。

    Electronic calculator
    82.
    发明授权
    Electronic calculator 失效

    公开(公告)号：US3896290A

    公开(公告)日：1975-07-22

    申请号：US43799174

    申请日：1974-01-30

    Applicant: ESTABLISSEMENT TELTEST R D

    Inventor： DENOUAL ROGER

    IPC: G07F7/10 ,  H04L9/32 ,  G06K7/00

    CPC classification number: G07F7/1016 ,  G06Q20/40 ,  G06Q40/00 ,  H04L9/32 ,  H04L9/34 ,  H04L2209/56

    Abstract: An electronic calculator for authenticating messages between financial institutions, e.g. banks, by utilizing a coded test number transmitted with the message. The calculator includes a set of memory codes to provide a numeral indicative of the message and a totalizer for the numerals in the code. The calculator enables the test numeral to be deciphered, either when sending or receiving, in an automatic fashion from programmed cards which may be made, checked, corrected or copied using the same machine.

    Multipath encoder-decoder arrangement
    83.
    发明授权
    Multipath encoder-decoder arrangement 失效
    多路编码器解码器布置

    公开(公告)号：US3657699A

    公开(公告)日：1972-04-18

    申请号：US3657699D

    申请日：1970-06-30

    Applicant: IBM

    Inventor： ROCHER EDOUARD Y ,  SCHUSTER STANLEY E

    IPC: G11C19/00 ,  G11C19/18 ,  H04K1/06 ,  H04L9/34 ,  G08C25/00

    CPC classification number: H04K1/06 ,  G11C19/00 ,  G11C19/184 ,  H04L9/0637 ,  H04L9/34 ,  H04L2209/12

    Abstract: A multipath encoder-decoder arrangement which consists of a plurality of storage devices such as memory cells, for example, which can be shifted from one series configuration into at least a second series configuration. The storage devices or at least a portion of them are switched from a first series path to a second series path. In one configuration, the outputs of all the storage devices are switched to the input of a succeeding storage device in a first path to the input of a different storage device in a second series path. In another embodiment, only a portion of the storage devices in one path are switched to form a series arrangement of storage devices in a second path in conjunction with fixed interconnections between certain other of the storage devices. By simply switching between paths, the order of information can be changed, i.e., interleaved, in such a way that errors which occur in bursts when transmitting data are spread out over the entire message with an inter-error space large enough to improve error correction. By providing control means which controls the shifting of data along the series configurations and the switching between configurations, in accordance with a given key, it is possible to scramble transmitted data at various levels of complexity. The complexity at one level, for example, is provided by a feedback loop connected between the input and output of the series configurations which permits data held in the series paths to be changed in both position and polarity. Another level of complexity can be achieved by modifying the key with another key which has been logically combined with previously transmitted encoded data. After transmission, the data is received and unscrambled in a similar encoder-decoder arrangement except that the decoding process is effectively reversed.

    Abstract translation: 一种多路径编码器 - 解码器装置，其由诸如存储器单元的多个存储装置组成，其可以从一个串联配置转移到至少第二个串联配置。 存储设备或其至少一部分从第一串行路径切换到第二串行路径。 在一种配置中，将所有存储设备的输出切换到第二路径中的不同存储设备的输入的第一路径中的后续存储设备的输入。 在另一个实施例中，只有一个路径中的一部分存储设备被切换以形成第二路径中的存储设备的串联布置，结合在某些其他存储设备之间的固定互连。 通过简单地在路径之间切换，信息的顺序可以被改变，即交织，使得在发送数据时在突发中出现的错误在整个消息中分散，具有足够大的错误间隔以改善纠错 。 通过提供控制装置，其控制沿着串联配置的数据移位和配置之间的切换，根据给定的键，可以以各种复杂程度对发送的数据进行加扰。 例如，一个级别的复杂性由连接在串联配置的输入和输出之间的反馈回路提供，其允许保持在串联路径中的数据在位置和极性两者上改变。 可以通过使用与先前发送的编码数据进行逻辑组合的另一个键修改密钥来实现另一个复杂度。 在传输之后，以类似的编码器 - 解码器装置接收和解扰数据，除了解码过程被有效地反转。

    CRYPTOGRAPHIC HASH GENERATED USING DATA PARALLEL INSTRUCTIONS
    86.
    发明申请
    CRYPTOGRAPHIC HASH GENERATED USING DATA PARALLEL INSTRUCTIONS 审中-公开

    公开(公告)号：US20180248687A1

    公开(公告)日：2018-08-30

    申请号：US15902820

    申请日：2018-02-22

    Applicant: GOOGLE LLC

    Inventor： Jan Wassenberg ,  Jyrki Antero Alakuijala

    IPC: H04L9/06 ,  H04L9/32 ,  H04L9/34 ,  G06F9/38

    CPC classification number: H04L9/0643 ,  G06F9/3887 ,  H04L9/3242 ,  H04L9/34

    Abstract: A fast cryptographic hash of an input file using multiplication and permutation operations in a parallel processing environment. An example method includes updating an internal state for each of a plurality of packets, the packets being read from an input file. Updating the state for a packet can include injecting the packet into an internal state, mixing the bits of the internal state using multiplication, and shuffling the result of the multiplication so that bits with highest quality are permuted to locations that will propagate most widely in a next multiplication operation. The method also includes performing a reduction on the internal state and repeating the update of the internal state, the reduction, and the injecting a second time. The method may further include finalizing the internal state and storing a portion of the final internal state as a cryptographic hash of the input file.

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