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公开(公告)号：US20180143805A1
公开(公告)日：2018-05-24
申请号：US15874642
申请日：2018-01-18
Applicant: Imagination Technologies Limited
Inventor： Leonard Rarick
CPC classification number: G06F7/52 , G06F7/552 , G06F7/5525 , G06F2207/5521
Abstract: A method and computer system are provided for performing a comparison computation, e.g. for use in a check procedure for a reciprocal square root operation. The comparison computation compares a multiplication of three values with a predetermined value. The computer system performs the multiplication using multiplier logic which is configured to perform multiply operations in which two values are multiplied together. A first and second of the three values are multiplied to determine a first intermediate result, w1. The digits of w1 are separated into two portions, w1,1 and w1,2. The third of the three values is multiplied with w1,2 and the result is added into a multiplication of the third of the three values with w1,1 to thereby determine the result of multiplying the three values together. In this way the comparison is performed with high accuracy, whilst keeping the area and power consumption of the multiplier logic low.
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公开(公告)号：US20180121167A1
公开(公告)日：2018-05-03
申请号：US15419757
申请日：2017-01-30
Applicant: Samsung Electronics Co., Ltd.
Inventor： Bonnie Collett SEXTON , James T. LONGINO
CPC classification number: G06F7/552 , G06F7/4824 , G06F7/49 , G06F7/535 , G06F17/17 , G06F2207/48 , G06F2207/552
Abstract: Apparatuses and methods of manufacturing same, systems, and methods for generating a starting estimate for radix-16 square root iterative calculation using hardware, including a radix-4 partial remainder-divisor (PD) table, which is used for both division and square root operations, are described. In one aspect, a part of a radicand for a radix-16 square root iterative operation is used to determine column/root and row/partial radicand values, which are then used to determine a starting estimate from a radix-4 PD table for the radix-16 square root iterative operation.
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公开(公告)号：US09875083B2
公开(公告)日：2018-01-23
申请号：US14452315
申请日：2014-08-05
Applicant: Imagination Technologies, Limited
Inventor： Leonard Rarick
CPC classification number: G06F7/52 , G06F7/552 , G06F7/5525 , G06F2207/5521
Abstract: A method and computer system are provided for performing a comparison computation, e.g. for use in a check procedure for a reciprocal square root operation. The comparison computation compares a multiplication of three values with a predetermined value. The computer system performs the multiplication using multiplier logic which is configured to perform multiply operations in which two values are multiplied together. A first and second of the three values are multiplied to determine a first intermediate result, w1. The digits of w1 are separated into two portions, w1,1 and w1,2. The third of the three values is multiplied with w1,2 and the result is added into a multiplication of the third of the three values with w1,1 to thereby determine the result of multiplying the three values together. In this way the comparison is performed with high accuracy, while keeping the area and power consumption of the multiplier logic low.
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84.发明申请
公开(公告)号：US20170307369A1
公开(公告)日：2017-10-26
申请号：US15423746
申请日：2017-02-03
Applicant: TOPCON CORPORATION
Inventor： You Sasaki , Kazuhiro Ogawa , Tadayuki Ito
Abstract: To carry out evaluation of a road surface property easily and in a short period of time without being costly. Measurement data of a road surface measured for a predetermined road width along a path of a road to be measured is acquired; a unit area having a preset length dimension along the path in the road width is set along the path; a model plane in the unit area is set based on the measurement data at each point in the unit area; point group data is generated from a spaced amount of the model plane and each point in the unit area, visualize and display the spaced amount in the path, and display a result of evaluation obtained through statistical processing with the path shown on a map.
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公开(公告)号：US20170269902A1
公开(公告)日：2017-09-21
申请号：US15611595
申请日：2017-06-01
Applicant: Imagination Technologies Limited
Inventor： Manouk Manoukian , Leonard Rarick
CPC classification number: G06F7/483 , G06F7/499 , G06F7/535 , G06F7/5525
Abstract: Method and computer system for implementing an operation on ≧1 floating point input, in accordance with a rounding mode, e.g. using a Newton-Raphson technique. The floating point result comprises a p-bit mantissa. An unrounded proposed mantissa result is determined using the Newton-Raphson technique, wherein a p-bit rounded proposed mantissa result, t, corresponds to a rounding of the unrounded proposed mantissa result in accordance with the rounding mode, with k leading zeroes. If an increment to the (m−k)th bit of the unrounded result would affect the p-bit rounded result then the input(s) and bits of the unrounded result are used to determine a check parameter which is indicative of a relationship between an exact result and the unrounded result if the (m−k)th bit were incremented. The p-bit mantissa of the floating point result, is determined in dependence upon the check parameter, to be either t or t+1.
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公开(公告)号：US09684489B2
公开(公告)日：2017-06-20
申请号：US13601709
申请日：2012-08-31
Applicant: Mitchell A. Thornton , Saurabh Gupta
Inventor： Mitchell A. Thornton , Saurabh Gupta
CPC classification number: G06F7/544 , G06F7/552 , G06F2207/5523
Abstract: Methods, apparatuses, and computer program products for squaring an operand include identifying a fixed-point value with a fixed word size and a substring size for substrings of the fixed-point value, wherein the fixed-point value comprises a binary bit string. A square of the fixed-point value can be determined using the fixed point value, the substring size, and least significant bits of the fixed-point value equal to the substring size.
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公开(公告)号：US20160147504A1
公开(公告)日：2016-05-26
申请号：US14551110
申请日：2014-11-24
Applicant: APPLE INC.
Inventor： Micha Anholt , Moti Teitel
CPC classification number: G06F7/724 , G06F7/552 , G06F7/5525 , G06F2207/5526
Abstract: A method includes receiving a first element of a Galois Field of order qm, where q is a prime number and m is a positive integer. The first element is raised to a predetermined power so as to form a second element z, wherein the predetermined power is a function of qm and an integer p, where p is a prime number which divides qm−1. The second element z is raised to a pth power to form a third element. If the third element equals the first element, the second element multiplied by a pth root of unity raised to a respective power selected from a set of integers between 0 and p−1 is output as at least one root of the first element.
Abstract translation: 一种方法包括接收秩序q m的伽罗瓦域的第一元素，其中q是素数，m是正整数。 将第一元件升高到预定的功率以形成第二元件z，其中预定功率是qm和整数p的函数，其中p是除以qm-1的素数。 第二元件z升高到第p个功率以形成第三元件。 如果第三元素等于第一元素，则将第二元素乘以第p个单位根提升到从0和p-1之间的整数集合中选择的相应功率作为第一元素的至少一个根。
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公开(公告)号：US20160147503A1
公开(公告)日：2016-05-26
申请号：US14549639
申请日：2014-11-21
Applicant: ARM LIMITED
Inventor： Neil BURGESS , David Raymond LUTZ
CPC classification number: G06F7/535 , G06F7/5375 , G06F7/5525 , G06F9/3001 , G06F2207/5351 , G06F2207/5528
Abstract: A processing apparatus has combined divide-square root circuitry for performing a radix-N SRT divide algorithm and a radix-N SRT square root algorithm, where N is an integer power-of-2. The combined circuitry has shared remainder updating circuitry which performs remainder updates for a greater number of iterations per cycle for the SRT divide algorithm than for the SRT square root algorithm. This allows reduced circuit area while avoiding the SRT square root algorithm compromising the performance of the SRT divide algorithm.
Abstract translation: 处理装置具有用于执行基数-N SRT除法算法和基数N SRT平方根算法的组合的分方根电路，其中N是2的整数幂。 组合电路具有共享余数更新电路，对于SRT除法算法而言，对于SRT平方根算法，每个周期执行更多次迭代的余数更新。 这允许减小电路面积，同时避免SRT平方根算法损害SRT除法算法的性能。
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89.发明申请SMALL MULTIPLIER AFTER INITIAL APPROXIMATION FOR OPERATIONS WITH INCREASING PRECISION 审中-公开经过初步的近似逼近后，小型多媒体操作员可以提高精度
公开(公告)号：US20160110163A1
公开(公告)日：2016-04-21
申请号：US14516643
申请日：2014-10-17
Applicant: Imagination Technologies, Limited
Inventor： Leonard Rarick
CPC classification number: G06F7/552 , G06F7/523 , G06F7/537 , G06F7/5525 , G06F2207/5351
Abstract: In an aspect, a processor includes circuitry for iterative refinement approaches, e.g., Newton-Raphson, to evaluating functions, such as square root, reciprocal, and for division. The circuitry includes circuitry for producing an initial approximation; which can include a LookUp Table (LUT). LUT may produce an output that (with implementation-dependent processing) forms an initial approximation of a value, with a number of bits of precision. A limited-precision multiplier multiplies that initial approximation with another value; an output of the limited precision multiplier goes to a full precision multiplier circuit that performs remaining multiplications required for iteration(s) in the particular refinement process being implemented. For example, in division, the output being calculated is for a reciprocal of the divisor. The full-precision multiplier circuit requires a first number of clock cycles to complete, and both the small multiplier and the initial approximation circuitry complete within the first number of clock cycles.
Abstract translation: 在一方面，处理器包括用于迭代细化方法（例如，Newton-Raphson）的用于评估诸如平方根，倒数和分割的函数的电路。 电路包括用于产生初始近似的电路; 其可以包括查找表（LUT）。 LUT可以产生（具有实现相关的处理）的输出，其形成具有多个精度位的值的初始近似值。 有限精度乘数将初始逼近与另一个值相乘; 有限精度乘法器的输出转到全精度乘法器电路，执行在所实现的特定细化过程中迭代所需的剩余乘法。 例如，在划分中，计算的输出是除数的倒数。 全精度乘法器电路需要第一数量的时钟周期来完成，并且小乘法器和初始近似电路都在第一数量的时钟周期内完成。
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90.发明授权Vector math instruction execution by DSP processor approximating division and complex number magnitude 有权DSP处理器的矢量数学指令执行近似分割和复数量级
公开(公告)号：US09015452B2
公开(公告)日：2015-04-21
申请号：US12708180
申请日：2010-02-18
Applicant: Udayan Dasgupta
Inventor： Udayan Dasgupta
CPC classification number: G06F9/30014 , G06F7/4806 , G06F7/535 , G06F7/548 , G06F7/552 , G06F9/30036 , G06F9/30065 , G06F9/3887 , G06F9/3891 , G06F2207/3828 , G06F2207/5354 , G06F2207/5525
Abstract: A digital signal processor (DSP) includes an instruction fetch unit, an instruction decode unit, a register set and a plurality of work units in communication with the instruction decode unit. A first embodiment calculates two divisions on packed numerators and packed denominators. The DSP work units calculate indexes into a 1/d look-up table and make a final sign correction. A second embodiment calculates an approximation of a vector magnitude of a complex number x+jy. The approximation is based upon √(x2+y2)≈α*max(|x|, |y|)+β*min(|x|, |y|). The DSP work units calculate the absolute values, find the maxima and minima, and form the packed results of two vector magnitude calculations.
Abstract translation: 数字信号处理器（DSP）包括与指令解码单元通信的指令获取单元，指令解码单元，寄存器组和多个工作单元。 第一实施例计算包装分子和包装分母上的两个部分。 DSP工作单元将索引计算到1 / d查找表中，并进行最终符号校正。 第二实施例计算复数x + jy的矢量幅度的近似。 近似值基于√（x2 + y2）≈α* max（| x |，| y |）+＆bgr; * min（| x |，| y |）。 DSP工作单元计算绝对值，找到最大值和最小值，并形成两个矢量幅度计算的压缩结果。
