公开(公告)号：US10109501B2

公开(公告)日：2018-10-23

申请号：US15693489

申请日：2017-09-01

申请人： FUJI ELECTRIC CO., LTD. ,  Octec, Inc.

发明人： Koh Yoshikawa ,  Haruo Nakazawa ,  Kenichi Iguchi ,  Yasukazu Seki ,  Katsuya Okumura

IPC分类号： H01L21/44 ,  H01L21/56 ,  H01L29/40 ,  H01L21/31 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L21/283 ,  H01L29/861 ,  H01L21/76 ,  H01L21/04 ,  H01L29/16 ,  H01L29/20

摘要： A semiconductor device having a voltage resistant structure in a first aspect of the present invention is provided, comprising a semiconductor substrate, a semiconductor layer on the semiconductor substrate, a front surface electrode above the semiconductor layer, a rear surface electrode below the semiconductor substrate, an extension section provided to a side surface of the semiconductor substrate, and a resistance section electrically connected to the front surface electrode and the rear surface electrode. The extension section may have a lower permittivity than the semiconductor substrate. The resistance section may be provided to at least one of the upper surface and the side surface of the extension section.

公开(公告)号：US10103067B1

公开(公告)日：2018-10-16

申请号：US15617388

申请日：2017-06-08

申请人： GLOBALFOUNDRIES Inc.

发明人： Peter Baars ,  Gunter Grasshoff ,  Rico Hueselitz

IPC分类号： H01L21/76 ,  H01L21/84 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L21/02 ,  H01L29/161 ,  H01L21/8238

摘要： A method of manufacturing a trench isolation of a semiconductor device is provided including providing a silicon-on-insulator (SOI) substrate comprising a semiconductor bulk substrate, a buried oxide layer formed on the semiconductor bulk substrate and a semiconductor layer formed on the buried oxide layer, forming a trench through the semiconductor layer and extending at least partially into the buried oxide layer, forming a liner at sidewalls of the trench, deepening the trench into the semiconductor bulk substrate, filling the deepened trench with a flowable dielectric material, and performing an anneal of the flowable dielectric material.

公开(公告)号：US10096518B2

公开(公告)日：2018-10-09

申请号：US15665651

申请日：2017-08-01

申请人： Semiconductor Manufacturing International (Shanghai) Corporation ,  Semiconductor Manufacturing International (Beijing) Corporation

发明人： Fei Zhou

IPC分类号： H01L21/76 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/762 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H01L27/11

摘要： Semiconductor structure and fabrication method thereof are provided. An exemplary method includes providing a semiconductor substrate including a plurality of first fin structures, each having a first width, and a plurality of second fin structures, each having a second width greater than the first width. The method further includes forming a first isolation film covering sidewall surfaces of the first fin structures and the second fin structures, forming a trench in the first isolation film to expose at least a top portion of at least one sidewall surface of one or more second fin structures, forming an isolation fluid layer to fill the trenches, and performing an oxygen annealing process to convert a surface layer of the top portion of the at least one sidewall surface of the one or more second fin structures into a by-product layer, and to convert the isolation fluid layer into a second isolation film.

公开(公告)号：US10096496B2

公开(公告)日：2018-10-09

申请号：US15495832

申请日：2017-04-24

申请人： Applied Materials, Inc.

发明人： Dmitry Lubomirsky ,  Srinivas Nemani ,  Ellie Yieh ,  Sergey G. Belostotskiy

IPC分类号： H01L21/76 ,  H01L21/67 ,  H01L21/3065 ,  H01J37/32 ,  C23C16/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/683 ,  H01L21/02

摘要： Methods and process chambers for etching of low-k and other dielectric films are described. For example, a method includes modifying portions of the low-k dielectric layer with a plasma process. The modified portions of the low-k dielectric layer are etched selectively over a mask layer and unmodified portions of the low-k dielectric layer. Etch chambers having multiple chamber regions for alternately generating distinct plasmas are described. In embodiments, a first charge coupled plasma source is provided to generate an ion flux to a workpiece in one operational mode, while a secondary plasma source is provided to provide reactive species flux without significant ion flux to the workpiece in another operational mode. A controller operates to cycle the operational modes repeatedly over time to remove a desired cumulative amount of the dielectric material.

公开(公告)号：US10083882B2

公开(公告)日：2018-09-25

申请号：US15608558

申请日：2017-05-30

申请人： International Business Machines Corporation

发明人： Karthik Balakrishnan ,  Pouya Hashemi ,  Sanghoon Lee

IPC分类号： H01L21/76 ,  H01L21/84 ,  H01L21/308 ,  H01L21/02 ,  H01L27/12 ,  H01L21/306 ,  H01L21/3105 ,  H01L29/66 ,  H01L29/04 ,  H01L29/423 ,  H01L29/06 ,  H01L29/20

CPC分类号： H01L21/845 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/02433 ,  H01L21/02538 ,  H01L21/02639 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/3081 ,  H01L21/31056 ,  H01L27/1211 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/6681 ,  H01L29/7853 ,  H01L29/78654 ,  H01L29/78681 ,  H01L29/78696

摘要： A method for forming a nanowire device comprises depositing a hard mask on portions of a silicon substrate having a orientation wherein the hard mask is oriented in the direction, etching the silicon substrate to form a mandrel having (111) faceted sidewalls; forming a layer of insulator material on the substrate; forming a sacrificial stack comprising alternating layers of sacrificial material and dielectric material disposed on the layer of insulator material and adjacent to the mandrel; patterning and etching the sacrificial stack to form a modified sacrificial stack adjacent to the mandrel and extending from the mandrel; removing the sacrificial material from the modified sacrificial stack to form growth channels; epitaxially forming semiconductor in the growth channels; and etching the semiconductor to align with the end of the growth channels and form a semiconductor stack comprising alternating layers of dielectric material and semiconductor material.

公开(公告)号：US10079305B2

公开(公告)日：2018-09-18

申请号：US14861748

申请日：2015-09-22

申请人： Samsung Electronics Co., Ltd.

发明人： Byeongchan Lee ,  Nam-Kyu Kim ,  JinBum Kim ,  Kwan Heum Lee ,  Choeun Lee ,  Sujin Jung

IPC分类号： H01L29/06 ,  H01L29/165 ,  H01L29/78 ,  H01L21/02 ,  H01L21/76 ,  H01L29/08 ,  H01L29/66

CPC分类号： H01L29/7851 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7848

摘要： Provided are a semiconductor device and a method of fabricating the same. The device may include an active pattern protruding from a substrate, gate structures crossing the active pattern, and a source/drain region provided between adjacent ones of the gate structures. The source/drain region may include a source/drain epitaxial layer in a recessed region, which is formed in the active pattern between the adjacent ones of the gate structures. Further, an impurity diffusion region may be provided in the active pattern to enclose the source/drain epitaxial layer along inner surfaces of the recessed region.

公开(公告)号：US10062543B2

公开(公告)日：2018-08-28

申请号：US15170881

申请日：2016-06-01

申请人： KLA-Tencor Corporation

发明人： Ajay Gupta ,  Thanh Huy Ha ,  Olivier Moreau ,  Kumar Raja

IPC分类号： G06K9/00 ,  H01L21/76 ,  G01B11/00 ,  H01L23/544 ,  G06F19/00 ,  H01J37/22 ,  G03F7/20

CPC分类号： H01J37/222 ,  G03F7/70633 ,  H01J2237/221 ,  H01J2237/24578 ,  H01J2237/31798

摘要： Methods and systems for determining overlay error between different patterned features of a design printed on a wafer in a multi-patterning step process are provided. For multi-patterning step designs, the design for a first patterning step is used as a reference and designs for each of the remaining patterning steps are synthetically shifted until the synthetically shifted designs have the best global alignment with the entire image based on global image-to-design alignment. The final synthetic shift of each design for each patterning step relative to the design for the first patterning step provides a measurement of relative overlay error between any two features printed on the wafer using multi-patterning technology.

公开(公告)号：US10049913B2

公开(公告)日：2018-08-14

申请号：US15484972

申请日：2017-04-11

申请人： Tokyo Electron Limited

发明人： Kandabara N. Tapily

IPC分类号： H01L21/76 ,  H01L21/762 ,  H01L21/02

摘要： Methods for void-free SiO2 filling of fine recessed features and selective SiO2 deposition on catalytic surfaces are described. According to one embodiment, the method includes providing a substrate containing recessed features, coating surfaces of the recessed features with a metal-containing catalyst layer, in the absence of any oxidizing and hydrolyzing agent, exposing the substrate at a substrate temperature of approximately 150° C. or less, to a process gas containing a silanol gas to deposit a conformal SiO2 film in the recessed features, and repeating the coating and exposing at least once to increase the thickness of the conformal SiO2 film until the recessed features are filled with SiO2 material that is void-free and seamless in the recessed features. In one example, the recessed features filled with SiO2 material form shallow trench isolation (STI) structures in a semiconductor device.

公开(公告)号：US10032863B2

公开(公告)日：2018-07-24

申请号：US15090000

申请日：2016-04-04

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Daniel Nelson Carothers ,  Jeffrey R. Debord

IPC分类号： H01L21/76 ,  H01L29/06 ,  H01L21/762 ,  H01L29/04 ,  H01L21/84 ,  H01L27/12 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/306 ,  H01L29/78

摘要： An integrated circuit may be formed by forming a buried isolation layer in an isolation recess in a single-crystal silicon-based substrate. Exposed lateral surfaces of the substrate at the buried isolation layer are covered with a dielectric sidewall. A seed trench is formed through the buried isolation layer to expose the substrate. A single-crystal silicon-based seed layer is formed through the seed trench, extending above the top surface of the buried isolation layer. A silicon-based non-crystalline layer is formed contacting the seed layer. A cap layer is formed over the non-crystalline layer. A radiant-induced recrystallization process converts the non-crystalline layer to a single-crystal layer aligned with the seed layer. The cap layer is removed and the single-crystal layer is planarized, leaving an isolated semiconductor layer over the buried isolation layer.

公开(公告)号：US10008449B2

公开(公告)日：2018-06-26

申请号：US15603831

申请日：2017-05-24

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Theodorus E. Standaert ,  Vamsi K. Paruchuri

IPC分类号： H01L23/52 ,  H01L21/76 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L21/288 ,  H01L21/02 ,  H01L21/3213

CPC分类号： H01L23/53238 ,  H01L21/02164 ,  H01L21/288 ,  H01L21/2885 ,  H01L21/32133 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76873 ,  H01L21/76874 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76886 ,  H01L23/528

摘要： A method of forming electrically conductive structures that includes forming a copper containing layer including a barrier forming element, and applying a first anneal to the copper containing layer. The first anneal increases grain size of the copper in the copper containing layer. The copper containing layer is etched to provide a plurality of copper containing lines. A dielectric fill is deposited in the space between adjacent copper containing lines. A second anneal is applied to the plurality of copper containing lines. During the second anneal the barrier forming element diffuse to an interface between sidewalls of the copper containing lines and the dielectric fill to form a barrier layer along the sidewalls of the copper containing lines.