公开(公告)号：US10914795B2

公开(公告)日：2021-02-09

申请号：US16280480

申请日：2019-02-20

Applicant: Crocus Technology Inc.

Inventor： Anuraag Mohan

IPC: G01R33/00 ,  G01R33/09

Abstract: A circuit has a magnetic sensor that produces an uncompensated magnetic sensor output signal. A temperature sensor produces an ambient temperature signal. A compensation circuit is connected to the magnetic sensor and the temperature sensor. The compensation circuit is configured to add a computed temperature compensation signal to the uncompensated magnetic sensor output signal to produce a magnetic sensor temperature compensated output signal that reduces thermally induced variation of the uncompensated magnetic sensor output signal.

公开(公告)号：US10460779B2

公开(公告)日：2019-10-29

申请号：US15891233

申请日：2018-02-07

Applicant: Crocus Technology Inc.

Inventor： Michael Gaidis ,  Thao Tran

IPC: G11C11/16 ,  H01L43/08 ,  H01F10/32 ,  H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: An apparatus has a reference magnetic tunnel junction with a high aspect ratio including a reference layer with magnetization along a minor axis and a storage layer with magnetization along a major axis. The storage layer magnetization is substantially perpendicular to the magnetization along the minor axis. The magnetization orientation between the minor axis and the major axis is maintained by shape anisotropy caused by the high aspect ratio.

公开(公告)号：US09228855B2

公开(公告)日：2016-01-05

申请号：US13787585

申请日：2013-03-06

Applicant: Crocus Technology Inc.

Inventor： Bertrand F. Cambou ,  Douglas J. Lee ,  Ken Mackay ,  Barry Hoberman

IPC: G01D5/12 ,  G01B7/30 ,  G01R33/09 ,  G01C17/02 ,  G01D5/16

CPC classification number: G01D5/12 ,  G01B7/30 ,  G01C17/02 ,  G01D5/16 ,  G01R33/0029 ,  G01R33/096 ,  G01R33/098 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

Abstract: An apparatus includes circuits, a field line configured to generate a magnetic field based on an input, a sensing module configured to determine a parameter of each circuit, and a magnetic field direction determination module configured to determine an angular orientation of the apparatus relative to an external magnetic field based on the parameter. Each circuit includes multiple magnetic tunnel junctions. Each magnetic tunnel junction includes a storage layer having a storage magnetization direction and a sense layer having a sense magnetization direction configured based on the magnetic field. Each magnetic tunnel junction is configured such that the sense magnetization direction and a resistance of the magnetic tunnel junction vary based on the external magnetic field. The parameter varies based on the resistances of the multiple magnetic tunnel junctions. The magnetic field direction determination module is implemented in at least one of a memory or a processing device.

公开(公告)号：US20150214953A1

公开(公告)日：2015-07-30

申请号：US14606967

申请日：2015-01-27

Applicant: Crocus Technology Inc.

Inventor： Douglas J. Lee ,  Yaron Oren-Pines ,  Stuart Desmond Rumley ,  Seyed A. Tabatabaei ,  Bertrand F. Cambou

IPC: H03K19/18

CPC classification number: H03K19/18 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  H01L21/822 ,  H03B15/006 ,  H03D7/00 ,  H03D2200/0074

Abstract: A circuit includes a magnetic logic unit including input terminals, output terminals, a field line, and magnetic tunnel junctions (MTJs). The field line electrically connects a first and a second input terminal, and is configured to generate a magnetic field based on an input to at least one of the first and the second input terminal. The input is based on a first analog input to the circuit. Each MTJ is electrically connected to a first and a second output terminal, and is configured such that an output of at least one of the first and the second output terminal varies in response to a combined resistance of the MTJs. The resistance of the MTJs varies based on the magnetic field. The circuit is configured to mix the first analog input and a second analog input to generate an analog output based on the output of the second output terminal.

Abstract translation: 电路包括包括输入端子，输出端子，场线和磁隧道结（MTJ）的磁逻辑单元。 场线电连接第一和第二输入端子，并且被配置为基于对第一和第二输入端子中的至少一个的输入产生磁场。 输入基于电路的第一个模拟输入。 每个MTJ电连接到第一和第二输出端，并且被配置为使得第一和第二输出端中的至少一个的输出响应于MTJ的组合电阻而变化。 MTJ的电阻根据磁场而变化。 电路被配置为混合第一模拟输入和第二模拟输入以基于第二输出端的输出产生模拟输出。

公开(公告)号：US08933750B2

公开(公告)日：2015-01-13

申请号：US13769156

申请日：2013-02-15

Applicant: Crocus Technology Inc.

Inventor： Bertrand F. Cambou ,  Douglas J. Lee ,  Ken Mackay

IPC: H03F15/00 ,  G11C11/02 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16

CPC classification number: H03F15/00 ,  G11C11/02 ,  G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H03F19/00

Abstract: An apparatus includes a circuit and a field line. The circuit includes a magnetic tunnel junction including a storage layer and a sense layer. The field line is configured to generate a magnetic field based on an input signal, where the magnetic tunnel junction is configured such that a magnetization direction of the sense layer and a resistance of the magnetic tunnel junction vary based on the magnetic field. The circuit is configured to amplify the input signal to generate an output signal that varies in response to the resistance of the magnetic tunnel junction.

Abstract translation: 一种装置包括电路和场线。 该电路包括一个包括存储层和感应层的磁性隧道结。 场线被配置为基于输入信号产生磁场，其中磁性隧道结被配置为使得感测层的磁化方向和磁性隧道结的电阻基于磁场而变化。 电路被配置为放大输入信号以产生响应于磁性隧道结的电阻而变化的输出信号。

公开(公告)号：US08816455B2

公开(公告)日：2014-08-26

申请号：US13657708

申请日：2012-10-22

Applicant: Crocus Technology, Inc.

Inventor： Neal Berger ,  Mourad El Baraji ,  Amitay Levi

IPC: H01L29/82

CPC classification number: H01L27/222 ,  G11C11/16 ,  G11C11/1673 ,  G11C11/1675 ,  H01L23/5226 ,  H01L23/528 ,  H01L29/82 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A memory device includes a magnetic layer including a plurality of magnetic random access memory (MRAM) cells, a first conductive layer, a layer including a strap connecting MRAM cells included in the plurality of MRAM cells, and a second conductive layer. The first conductive layer includes a conductive portion electrically connected to at least one of the plurality of MRAM cells, and a field line configured to write data to the at least one of the plurality of MRAM cells. The second conductive layer includes a conductive interconnect electrically connected to the at least one of the plurality of MRAM cells, where the magnetic layer is disposed between the first conductive layer and the second conductive layer. At least one of the plurality of MRAM cells is directly attached to the second conductive layer and the strap.

Abstract translation: 存储器件包括包括多个磁随机存取存储器（MRAM）单元的磁性层，第一导电层，包括连接多个MRAM单元中包括的MRAM单元的带的层和第二导电层。 第一导电层包括电连接到多个MRAM单元中的至少一个的导电部分，以及被配置为将数据写入多个MRAM单元中的至少一个的场线。 第二导电层包括电连接到多个MRAM单元中的至少一个MRAM单元的导电互连，其中磁性层设置在第一导电层和第二导电层之间。 多个MRAM单元中的至少一个直接附接到第二导电层和带。

公开(公告)号：US08717794B2

公开(公告)日：2014-05-06

申请号：US13309369

申请日：2011-12-01

Applicant: Bertrand F. Cambou ,  Neal Berger ,  Mourad El Baraji

Inventor： Bertrand F. Cambou ,  Neal Berger ,  Mourad El Baraji

IPC: G11C15/02

CPC classification number: G06F11/08 ,  G06F7/02 ,  G06F2207/025 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C15/02 ,  G11C15/046

Abstract: A check engine includes a plurality of comparators each including a first directional characteristic aligned to store at least one reference bit included in a set of reference bits, and a second directional characteristic aligned to present at least one target bit included in a set of target bits. Each of the plurality of comparators is configured to produce an output representing a level of matching between the at least one target bit and the at least one reference bit, based on a relative alignment between the first directional characteristic and the second directional characteristic. The check engine is configured such that the outputs of the plurality of comparators are combined to produce a combined output. The check engine is configured to determine that the set of target bits matches the set of reference bits based on the combined output of the plurality of comparators.

Abstract translation: 检查引擎包括多个比较器，每个比较器包括对齐以存储包括在一组参考比特中的至少一个参考比特的第一方向特性，以及对准以呈现包括在一组目标比特中的至少一个目标比特的第二方向特性 。 多个比较器中的每一个被配置为基于第一方向特性和第二方向特性之间的相对对准来产生表示所述至少一个目标位和所述至少一个参考位之间的匹配水平的输出。 检查引擎被配置为使得多个比较器的输出被组合以产生组合输出。 检查引擎被配置为基于多个比较器的组合输出来确定目标比特的集合与参考比特集匹配。

公开(公告)号：US20130288392A1

公开(公告)日：2013-10-31

申请号：US13848641

申请日：2013-03-21

Applicant: Crocus Technology Inc.

Inventor： Jean Pierre Nozieres ,  Jason Reid

IPC: H01L43/02

CPC classification number: H01L43/02 ,  G11C11/16 ,  H01L21/00 ,  H01L27/00 ,  H01L43/12

Abstract: Disclosed herein is a method of forming electronic device having thin-film components by using trenches. One or more of thin-film components is formed by depositing a thin-film in the trench followed by processing the deposited thin-film to have the desired thickness.

Abstract translation: 本文公开了通过使用沟槽形成具有薄膜部件的电子器件的方法。 通过在沟槽中沉积薄膜而形成薄膜成分中的一种或多种，​​然后将沉积的薄膜加工成具有所需的厚度。

公开(公告)号：US20130094283A1

公开(公告)日：2013-04-18

申请号：US13648221

申请日：2012-10-09

Applicant: CROCUS TECHNOLOGY, INC.

Inventor： Neal Berger ,  Jean-Pierre Nozieres ,  Virgile Javerliac

IPC: G11C11/16

CPC classification number: G11C11/1675 ,  G11C8/08 ,  G11C11/1659 ,  G11C11/1693

Abstract: A memory device includes a plurality of magnetic random access memory (MRAM) cells, a field line, and a field line controller configured to generate a write sequence that traverses the field line. The write sequence is for writing a multi-bit word to the plurality of MRAM cells. The multi-bit word includes a first subset of bits having a first polarity and a second subset of bits having a second polarity. The write sequence writes concurrently to at least a subset of the plurality of MRAM cells corresponding to the first subset of bits having the first polarity, then subsequently writes concurrently to a remaining subset of the plurality of MRAM cells corresponding to the second subset of bits having the second polarity.

Abstract translation: 一种存储器件包括多个磁性随机存取存储器（MRAM）单元，一个场线，以及一个现场线控制器，被配置为产生穿过场线的写入序列。 写入序列用于将多位字写入多个MRAM单元。 多位字包括具有第一极性的位的第一子集和具有第二极性的位的第二子集。 所述写入顺序并行地写入与具有所述第一极性的所述第一第一子集对应的所述多个MRAM单元的至少一个子集，然后并行地写入所述多个MRAM单元的对应于具有 第二极性。

公开(公告)号：US20120314487A1

公开(公告)日：2012-12-13

申请号：US13158312

申请日：2011-06-10

Applicant: Mourad El Baraji ,  Neal Berger ,  Lucien Lombard ,  Lucian Prejbeanu ,  Ricardo Alves Ferreira Costa E Sousa ,  Guillaume Prenat

Inventor： Mourad El Baraji ,  Neal Berger ,  Lucien Lombard ,  Lucian Prejbeanu ,  Ricardo Alves Ferreira Costa E Sousa ,  Guillaume Prenat

IPC: G11C11/416

CPC classification number: G11C11/5607 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/1675

Abstract: A magnetic random access memory (“MRAM”) cell includes: (1) a first magnetic layer having a first magnetization direction and a magnetic anisotropy axis; (2) a second magnetic layer having a second magnetization direction; and (3) a spacer layer disposed between the first magnetic layer and the second magnetic layer. The MRAM cell also includes a field line magnetically coupled to the MRAM cell and configured to induce a write magnetic field along a magnetic field axis, and the magnetic anisotropy axis is tilted relative to the magnetic field axis. During a write operation, the first magnetization direction is switchable between m directions to store data corresponding to one of m logic states, with m>2, at least one of the m directions is aligned relative to the magnetic anisotropy axis, and at least another one of the m directions is aligned relative to the magnetic field axis.

Abstract translation: 磁性随机存取存储器（MRAM）单元包括：（1）具有第一磁化方向和磁各向异性轴的第一磁性层; （2）具有第二磁化方向的第二磁性层; 和（3）设置在第一磁性层和第二磁性层之间的间隔层。 MRAM单元还包括磁耦合到MRAM单元并且被配置为沿着磁场轴诱导写磁场的磁场线，并且磁各向异性轴相对于磁场轴倾斜。 在写入操作期间，第一磁化方向可以在m个方向之间切换以存储对应于m个逻辑状态中的一个的数据，其中m≥2，m个方向中的至少一个相对于磁各向异性轴对准，并且至少另一个 m个方向中的一个相对于磁场轴线对准。