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公开(公告)号：US20230268405A1
公开(公告)日：2023-08-24
申请号：US17704022
申请日：2022-03-25
发明人： Chu-Kuang Liu
IPC分类号： H01L29/423 , H01L29/739 , H01L29/06
CPC分类号： H01L29/4236 , H01L29/7397 , H01L29/0696
摘要： A trench power semiconductor device includes a substrate, an epitaxial layer, a drain, a first active device, a second active device, and isolation trench structures. The epitaxial layer and the drain are disposed on two surfaces of the substrate, respectively. The first active device is disposed in a first portion of the epitaxial layer and has a first source and a first gate. The second active device is disposed in a second portion of the epitaxial layer and has a second source and a second gate. The isolation trench structures are disposed between the first portion and the second portion of the epitaxial layer to electrically isolate the first active device and the second active device. Each of the isolation trench structures includes a polysilicon structure with a floating potential and an insulating layer. The insulating layer is between the polysilicon structure and the epitaxial layer.
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公开(公告)号：US20210202701A1
公开(公告)日：2021-07-01
申请号：US16830225
申请日：2020-03-25
发明人： Chu-Kuang Liu , Yi-Lun Lo
IPC分类号： H01L29/10 , H01L29/78 , H01L21/225 , H01L21/265 , H01L21/324 , H01L29/66
摘要： A trench MOSFET and a manufacturing method of the same are provided. The trench MOSFET includes a substrate, an epitaxial layer having a first conductive type, a gate in a trench in the epitaxial layer, a gate oxide layer, a source region having the first conductive type, and a body region and an anti-punch through region having a second conductive type. The anti-punch through region is located at an interface between the source region and the body region, and a doping concentration thereof is higher than that of the body region. The epitaxial layer has a first pn junction near the source region and a second pn junction near the substrate. N regions are divided into N equal portions between the two pn junctions, and N is an integer greater than 1. The closer the N regions are to the first pn junction, the greater the doping concentration thereof is.
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公开(公告)号：US10892675B2
公开(公告)日：2021-01-12
申请号：US16104957
申请日：2018-08-20
发明人： Ching-Tsan Lee , Pei-Ting Yang , Ming-Hung Chien
IPC分类号： G05F1/569 , H02M1/08 , H02H3/00 , H03K17/081 , H02H3/18 , H03K17/0412
摘要： A voltage converting circuit and a control circuit thereof are provided. The control circuit includes a comparator, a clock generator, and a boost circuit. The comparator compares an input voltage with an output voltage to generate a comparison signal. The clock generator generates a clock signal according to the comparison signal to enable the clock signal to have a first frequency in a first time interval and to have a second frequency in a second time interval. The first frequency is higher than the second frequency. The first time interval occurs before the second time interval. The boost circuit receives the clock signal, pulls up a control signal of a driving switch in the first time interval according to a first driving capability, and generates the control signal in the second time interval according to a second driving capability. The first driving capability is greater than the second driving capability.
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4.发明申请公开(公告)号：US20200212197A1
公开(公告)日：2020-07-02
申请号：US16361217
申请日：2019-03-22
发明人： Chu-Kuang Liu , Hung-Kun Yang
IPC分类号： H01L29/66 , H01L21/308 , H01L21/02 , H01L29/20 , H01L29/205 , H01L29/778
摘要： A method of manufacturing a gate structure for gallium nitride (GaN) high electron mobility transistor (HEMT) includes orderly forming a channel layer, a barrier layer, a doped GaN layer, an undoped GaN layer, and an insulating layer on a substrate, and then removing a portion of the insulating layer to form a trench. A gate metal layer is formed on the substrate to cover the insulating layer and the trench, and then a mask layer aligned with the trench is formed on the gate metal layer, wherein the mask layer partially overlaps the insulating layer. By using the mask layer as an etching mask, the exposed gate metal layer and the underlying insulating layer, the undoped GaN layer and the doped GaN layer are removed, and then the mask layer is removed.
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公开(公告)号：US10388784B2
公开(公告)日：2019-08-20
申请号：US15455144
申请日：2017-03-10
发明人： Chu-Kuang Liu
IPC分类号： H01L29/78 , H01L29/06 , H01L29/423
摘要： A power chip and a transistor structure thereof are provided. The transistor structure includes a semiconductor substrate, a plurality of gate structures, a plurality of first doped regions and a second doped region. The gate structures are disposed on the semiconductor substrate. The first doped regions are formed respectively in a plurality of first areas surrounded by the gate structures. The second doped region is formed in a second area among the gate structures. Each of the gate structures is arranged in an enclosed ring, and the shape of each of the gate structures is octagon.
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公开(公告)号：US10218344B1
公开(公告)日：2019-02-26
申请号：US16121646
申请日：2018-09-05
发明人： Ching-Tsan Lee , Pei-Ting Yang
IPC分类号： H03K17/042 , H03K17/082
摘要： A voltage conversion circuit and a control circuit thereof are provided. The control circuit includes a voltage selection circuit, a buffer circuit, and a pull-down switch. The voltage selection circuit receives an input voltage and an output voltage, and selects a smaller voltage value as a selected voltage from the input voltage and the output voltage. The buffer circuit receives the selected voltage, and provides the selected voltage as a reference voltage. A control end of the pull-down switch receives an enable signal, so that the pull-down switch is switched on or switched off based on the enable signal. The pull-down switch is switched on based on the enable signal, to pull down a voltage at a control end of a driver switch to the reference voltage and switch off the driver switch.
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公开(公告)号：US20180302001A1
公开(公告)日：2018-10-18
申请号：US16018081
申请日：2018-06-26
发明人： Poyu Yang
CPC分类号： H02M3/33592 , H02M1/38 , Y02B70/1475
摘要： A power conversion apparatus including a transformer, a synchronous rectification (SR) transistor and an SR control circuit is provided. A first terminal of a primary side of the transformer receives an input voltage, and a first terminal of a secondary side outputs a DC voltage. A drain terminal of the SR transistor is coupled to a second terminal of the secondary side of the transformer. A source terminal of the SR transistor is coupled to a ground terminal. The SR control circuit receives a signal of the drain terminal of the SR transistor to serve it as a detection signal and generate a duty cycle signal. The SR control circuit converts the duty signal into a charging current and a discharging current so as to charge and discharge an energy-storage device and generate a first voltage. The SR control circuit turns off the SR transistor according to the first voltage.
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公开(公告)号：US09761464B2
公开(公告)日：2017-09-12
申请号：US14727872
申请日：2015-06-02
发明人： Yi-Chi Chang
IPC分类号： H01L23/053 , H01L21/48 , H01L21/78 , H01L23/00
CPC分类号： H01L21/4853 , H01L21/486 , H01L21/78 , H01L24/03 , H01L24/05 , H01L24/13 , H01L2224/02371 , H01L2224/02372 , H01L2224/03 , H01L2224/0345 , H01L2224/0346 , H01L2224/0347 , H01L2224/03914 , H01L2224/0401 , H01L2224/05572 , H01L2224/05582 , H01L2224/05611 , H01L2224/05639 , H01L2224/11 , H01L2224/131 , H01L2224/94 , H01L2924/00014 , H01L2924/014
摘要： A power MOSFET includes a substrate, a dielectric layer, solder balls, first and second patterned-metal layers. The substrate includes an active surface, a back surface, a source region and a gate region on the active surface, and a drain region on the back surface. The first patterned-metal layer disposed on the active surface includes a source electrode, a gate electrode, a drain electrode and a connecting trace. The source and gate electrodes electrically connect the source and gate regions. The connecting trace located at an edge of the substrate electrically connects the drain electrode. The dielectric layer disposed on the active surface exposes the first patterned-metal layer. The second patterned-metal layer includes UBM layers covering the source, gate and drain electrodes and a connecting metal layer covering the connecting trace and extending to the edge to electrically connect the drain region. The solder balls are disposed on the UBM layers.
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公开(公告)号：US20140225578A1
公开(公告)日：2014-08-14
申请号：US13762376
申请日：2013-02-08
发明人： Pao-Chuan Lin , Li-Chieh Chen , Hung-Che Chou
IPC分类号： G05F1/445
CPC分类号： G05F1/445 , H02M3/156 , H02M2001/0025
摘要： A voltage converter is disclosed. The voltage converter includes a constant on time signal generator, a first and second transistors, an inductor, a feedback circuit and a ripple injection circuit. The constant on time signal generator generates a first and second driving signals for driving the first and second transistors. The voltage converter generates an output signal at an output end thereof. The feedback circuit divides the output signal to generate a feedback signal at a feedback end of the voltage converter. The ripple injection circuit gets the voltage of the feedback end and the voltage of the phase end to generate a injection signal. The constant on time signal generator generates the first and second driving signals according to the injection signal, the output signal and a reference signal.
摘要翻译： 公开了电压转换器。 电压转换器包括恒定的导通时间信号发生器，第一和第二晶体管，电感器，反馈电路和纹波注入电路。 恒定的时间信号发生器产生用于驱动第一和第二晶体管的第一和第二驱动信号。 电压转换器在其输出端产生输出信号。 反馈电路将输出信号分开，以在电压转换器的反馈端产生反馈信号。 纹波注入电路获得反馈端的电压和相位端的电压以产生注入信号。 恒定的导通时间信号发生器根据注入信号，输出信号和参考信号产生第一和第二驱动信号。
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公开(公告)号：US08421180B2
公开(公告)日：2013-04-16
申请号：US13480491
申请日：2012-05-25
申请人： Chu-Kuang Liu
发明人： Chu-Kuang Liu
IPC分类号： H01L29/78
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/1095 , H01L29/407 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66143 , H01L29/66727 , H01L29/66734 , H01L29/782 , H01L29/872
摘要： A semiconductor structure is provided. A second area is disposed between first and third areas. An epitaxial layer is on a substrate. A body layer is in the epitaxial layer in first and second areas. First and second gates are in the body layer and in a portion of the epitaxial layer. The first gate is in the substrate and partially in first and second areas. The second gate is in the substrate and partially in second and third areas. A first contact plug is in a portion of the body layer in the first area. A second contact plug is at least in the epitaxial layer in the third area and contacts the epitaxial layer and the second gate. The first contact plug is electrically connected to the second contact plug. A first doped region is in the body layer between the first contact plug and the first gate.
摘要翻译： 提供半导体结构。 第二区域设置在第一和第三区域之间。 外延层位于基板上。 体层位于第一和第二区域的外延层中。 第一和第二栅极位于体层中并在外延层的一部分中。 第一个栅极位于基板中，部分位于第一和第二区域。 第二个栅极位于基板中，部分位于第二和第三区域。 第一接触塞在第一区域的身体层的一部分中。 第二接触插塞至少在第三区域的外延层中并与外延层和第二栅极接触。 第一接触插头电连接到第二接触插头。 第一掺杂区域位于第一接触插塞和第一栅极之间的体层中。
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