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2108 条记录 (耗时 0.04 秒)

    Data inversion circuit to perform DBI-DC encoding using PAM 4 signal
    5.
    发明授权
    Data inversion circuit to perform DBI-DC encoding using PAM 4 signal 有权

    公开(公告)号：US12126473B2

    公开(公告)日：2024-10-22

    申请号：US17896549

    申请日：2022-08-26

    申请人： Industry-University Cooperation Foundation Hanyang University

    发明人： Jaeduk Han ,  Eunji Song ,  SangHun Lee ,  YunSeong Jo ,  HyeongMin Seo ,  Hyuntae Kim

    IPC分类号： H04L25/49

    CPC分类号： H04L25/4917

    摘要： According to an aspect, a data inversion circuit configured to perform DBI-DC encoding using a PAM 4 signal may comprise a data generation unit configured to generate input data based on the PAM 4 signal and a data transmission unit comprising, an auxiliary signal generation unit configured to generate an auxiliary signal that determines whether to perform encoding on the input data by analyzing a plurality of data symbols included in the input data, a channel comprising a plurality of data lines and a data encoding unit configured to generate encoded data by performing DBI (data bus inversion) encoding on the data based on the auxiliary signal and to transmit the generated encoded data to a data reception unit via the channel.

    Flexible mechanism
    6.
    发明授权
    Flexible mechanism 有权

    公开(公告)号：US12122043B2

    公开(公告)日：2024-10-22

    申请号：US17184748

    申请日：2021-02-25

    申请人： INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY ERICA CAMPUS

    发明人： Byung-Ju Yi ,  Hwantaek Ryu

    IPC分类号： B25J15/12 ,  B25J9/10

    CPC分类号： B25J15/12 ,  B25J9/1045

    摘要： Disclosed is a flexible mechanism including: a backbone extending in a lengthwise direction thereof; a first steering wire group including one or more steering wires disposed in a spiral direction of a first direction along the lengthwise direction of the backbone and configured to transfer a handling force applied to ends thereof to an end effector; and a second steering wire group including one or more steering wires disposed in a spiral direction of a second direction, which is different from the first direction, along the lengthwise direction of the backbone and configured to transfer a handling force applied to ends thereof to the end effector.

    Clock data recovery circuits and electronic systems that support data-based clock recovery
    8.
    发明授权
    Clock data recovery circuits and electronic systems that support data-based clock recovery 有权

    公开(公告)号：US12119829B2

    公开(公告)日：2024-10-15

    申请号：US18308754

    申请日：2023-04-28

    申请人： Samsung Electronics Co., Ltd.

    发明人： Dongho Choi ,  Jaeduk Han ,  Yongho Song ,  Youngho Kwak ,  Gaeryun Sung ,  Dongju Yang ,  Kwanghee Choi ,  Hyeongmin Seo

    IPC分类号： H03L7/08 ,  H03L7/091 ,  H03L7/099

    CPC分类号： H03L7/0807 ,  H03L7/091 ,  H03L7/0998

    摘要： A clock data recovery circuit includes a phase-locked loop configured to generate a plurality of clock signals having unequal phases relative to each other, in response to a received clock signal, and a phase interpolator configured to interpolate phases of the plurality of clock signals during generation of multiphase sampling clock signals. A sampling clock adjustment circuit is also provided, which is configured to generate a plurality of data symbols by sampling a received data signal at sampling time points of the multiphase sampling clock signals, and further configured to: detect, from the plurality of data symbols, a first data pattern set to have a transition point immediately before a first reference data symbol, and a second data pattern set to have a transition point immediately after a second reference data symbol, detect a first signal level of the first data pattern at a sampling time point for sampling the first reference data symbol, detect a second signal level of the second data pattern at a sampling time point for sampling the second reference data symbol, and adjust phases of the multiphase sampling clock signals according to a result of comparing the first signal level to the second signal level.

    Current mode logic circuit
    10.
    发明授权
    Current mode logic circuit 有权

    公开(公告)号：US12107577B2

    公开(公告)日：2024-10-01

    申请号：US17802555

    申请日：2020-12-09

    申请人： Industry-University Cooperation Foundation Hanyang University

    发明人： Jae Duk Han

    IPC分类号： H03K19/0185 ,  H03K19/003 ,  H03K19/017

    CPC分类号： H03K19/01735 ,  H03K19/00361 ,  H03K19/00384

    摘要： According to an aspect, a current mode logic circuit comprise a first transistor to which an input voltage is applied, a second transistor connected in parallel with the first transistor; and a voltage sampling circuit which is connected to the first transistor and the second transistor and resets an output voltage output by integrating the input voltage for a predetermined set time (T) in a manner in which the output voltage is integrated in a direction opposite to a direction in which the input voltage is integrated for the predetermined set time (T).