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公开(公告)号：US12132122B2
公开(公告)日：2024-10-29
申请号：US18136698
申请日：2023-04-19
发明人： Guang Zeng , Moritz Hauf , Anton Mauder
IPC分类号： H01L29/861 , H01L29/06 , H01L29/66
CPC分类号： H01L29/861 , H01L29/0607 , H01L29/6609
摘要： A single chip power diode includes a semiconductor body having an anode region coupled to a first load terminal and a cathode region coupled to a second load terminal. An edge termination region surrounding an active region is terminated by a chip edge. The semiconductor body thickness is defined by a distance between at least one first interface area formed between the first load terminal and the anode region and a second interface area formed between the second load terminal and the cathode region. At least one inactive subregion is included in the active region. Each inactive subregion: has a blocking area with a minimal lateral extension of at least 20% of a drift region thickness; configured to prevent crossing of the load current between the first load terminal and the semiconductor body through the blocking area; and at least partially not arranged adjacent to the edge termination region.
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公开(公告)号：US12119400B2
公开(公告)日：2024-10-15
申请号：US17714660
申请日：2022-04-06
发明人： Robert Paul Haase , Jyotshna Bhandari , Heimo Hofer , Ling Ma , Ashita Mirchandani , Harsh Naik , Martin Poelzl , Martin Henning Vielemeyer , Britta Wutte
IPC分类号： H01L29/78 , H01L29/423 , H01L29/45 , H01L29/66
CPC分类号： H01L29/7813 , H01L29/4236 , H01L29/456 , H01L29/66734
摘要： A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.
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公开(公告)号：US12119376B2
公开(公告)日：2024-10-15
申请号：US16587631
申请日：2019-09-30
发明人： Armin Willmeroth , Franz Hirler , Bjoern Fischer , Joachim Weyers
IPC分类号： H01L29/78 , H01L29/06 , H01L29/40 , H02M1/08 , H01L29/10 , H01L29/423 , H02M1/00 , H02M3/155
CPC分类号： H01L29/0634 , H01L29/402 , H01L29/7802 , H01L29/7809 , H01L29/7811 , H01L29/7813 , H02M1/08 , H01L29/0615 , H01L29/0623 , H01L29/063 , H01L29/0649 , H01L29/1095 , H01L29/4238 , H02M1/0054 , H02M3/155
摘要： A switched-mode power supply includes a power semiconductor device that includes a semiconductor body comprising transistor cells and a drift zone between a drain layer and the transistor cells, the transistor cells comprising source zones, wherein the device exhibits a first output charge gradient when a voltage between the drain layer and the source zones of the transistor cells increases from a depletion voltage of the semiconductor device to a maximum drain/source voltage of the semiconductor device, wherein the device exhibits a second output charge gradient when a voltage between the drain layer and the source zones of the semiconductor device decreases from the maximum drain/source voltage to the depletion voltage of the semiconductor device, and wherein the semiconductor device is configured such that the first output charge gradient deviates by less than 5% from the second output charge gradient.
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公开(公告)号：US12119284B2
公开(公告)日：2024-10-15
申请号：US17690616
申请日：2022-03-09
发明人： Alexander Roth
IPC分类号： H01L23/373 , H01L21/48 , H01L23/00 , H01L23/15 , H01L23/367 , H01L23/498
CPC分类号： H01L23/3735 , H01L21/4846 , H01L21/4857 , H01L23/15 , H01L23/367 , H01L23/49894 , H01L24/30 , H01L24/33
摘要： A DBC substrate for power semiconductor devices includes a ceramic workpiece of a non-oxide ceramic having first and second opposing main sides, the ceramic workpiece having a thickness of 10 μm or more measured between the first and second main sides, a copper-containing layer disposed over the first main side, the copper-containing layer having a thickness of 5 μm or more, and an intermediate layer comprising Al2O3 disposed between the ceramic workpiece and the copper-containing layer.
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公开(公告)号：US20240313105A1
公开(公告)日：2024-09-19
申请号：US18603270
申请日：2024-03-13
IPC分类号： H01L29/78 , H01L21/762 , H01L23/528 , H01L29/08 , H01L29/66
CPC分类号： H01L29/7804 , H01L21/76224 , H01L23/528 , H01L29/0878 , H01L29/66712
摘要： The disclosure relates to a semiconductor die with a semiconductor body. The semiconductor die includes a vertical transistor device formed in a first area of the semiconductor body. The vertical transistor device includes a source region at a first side of the semiconductor body and a drain region at a second side of the semiconductor body. The semiconductor die further includes a first electrical isolation between the first area and a second area of the semiconductor body, and a diode in the second area of the semiconductor body. A cathode contact of the diode is electrically connected to the source region of the vertical transistor device.
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6.发明公开公开(公告)号：US20240312936A1
公开(公告)日：2024-09-19
申请号：US18604787
申请日：2024-03-14
发明人： Joon Shyan Tan , Lee Shuang Wang , Azlina Kassim , Teck Sim Lee , Kok Yau Chua , Chee Hong Lee , Zhihui Yuan
IPC分类号： H01L23/00 , H01L23/31 , H01L23/498 , H01L25/00 , H01L25/065
CPC分类号： H01L24/08 , H01L23/3107 , H01L23/49838 , H01L25/0655 , H01L25/50 , H01L24/45 , H01L24/48 , H01L2224/08225 , H01L2224/45014 , H01L2224/48175 , H01L2924/181 , H01L2924/19041 , H01L2924/19043 , H01L2924/19101
摘要： A power semiconductor package includes: a first power semiconductor die arranged on and electrically coupled to a first side of a first die pad; a first passive electronic component having a first end and an opposite second end, the first end being arranged on and coupled to the first side of the first die pad and the second end being coupled to an internal ledge of a first external contact; a second passive electronic component connected in series with the first passive electronic component; and an encapsulation encapsulating the first power semiconductor die and the first and second passive electronic components. The first external contact is exposed from a first lateral side of the encapsulation.
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公开(公告)号：US20240288213A1
公开(公告)日：2024-08-29
申请号：US18437366
申请日：2024-02-09
发明人： Clemens Rössler , Klemens Karl Heinrich Schüppert , Matthias German Dietl , Yves Colombe , Silke Katharina Auchter
CPC分类号： F25D19/006 , G21K1/003
摘要： A cryostat socket for holding an ion trap device mounted on a substrate in a cryostat includes a frame having a heat removal surface configured to be thermally coupled to a laterally outer region of the device carrier. The cryostat socket further includes a cover configured to exert a compressive force on the front side of the device carrier when assembled with the frame, by which the rear side of the device carrier is thermally coupled to the heat removal surface.
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公开(公告)号：US12074555B2
公开(公告)日：2024-08-27
申请号：US17863751
申请日：2022-07-13
发明人： Hannes Mathias Geike
摘要： A method of passively braking a motor to reduce a current motor speed includes generating at least one control signal to control a first load current generated by a first half bridge circuit and a second load current generated by a second half bridge circuit. During passive braking, the method includes synchronously driving a first high-side transistor and a second high-side transistor between their respective switching states at an alternating shorting frequency such that they are simultaneously in a same switching state, and synchronously driving a first low-side transistor and a second low-side transistor between their respective switching states at the alternating shorting frequency such that they are simultaneously in a same switching state, wherein the first high-side transistor and the second high-side transistor are driven in a complementary manner to the first low-side transistor and the second low-side transistor according to a predetermined duty cycle.
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公开(公告)号：US20240280614A1
公开(公告)日：2024-08-22
申请号：US18443446
申请日：2024-02-16
发明人： Giuseppe Bernacchia
CPC分类号： G01R19/32 , G01R19/0046
摘要： An integrated circuit is presented. The integrated circuit includes a first terminal, a second terminal, a control terminal, a current monitor terminal, a power transistor coupled between the first terminal and the second terminal, and a replica transistor coupled between the first terminal and the current monitor terminal. The integrated circuit is configured to control a current between the first terminal and the second terminal based on a control signal applied to the control terminal. The integrated circuit is further configured to provide, at the current monitor terminal, a current monitor signal indicative of a value of the current.
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公开(公告)号：US20240275379A1
公开(公告)日：2024-08-15
申请号：US18631931
申请日：2024-04-10
发明人： Markus Bina , Jens Barrenscheen , Anton Mauder
IPC分类号： H03K17/567 , H01L29/08 , H01L29/10 , H01L29/20 , H01L29/40 , H01L29/417 , H01L29/423 , H01L29/739 , H01L29/76 , H01L29/778 , H01L29/78 , H03K17/687
CPC分类号： H03K17/567 , H01L29/0895 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/7397 , H01L29/7606 , H01L29/7786 , H01L29/7788 , H01L29/7813 , H01L29/7831 , H03K17/687 , H01L29/1066 , H01L29/2003 , H03K2017/6878
摘要： In accordance with an embodiment, a method includes switching on a transistor device by generating a first conducting channel by driving a first gate electrode and, before generating the first conducting channel, generating a second conducting channel by driving a second gate electrode, wherein the second gate electrode is adjacent the first gate electrode in a current flow direction of the transistor device.
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