公开(公告)号：US12191302B2

公开(公告)日：2025-01-07

申请号：US17357000

申请日：2021-06-24

Applicant: Infineon Technologies Americas Corp.

Inventor： Michael A. Briere

IPC: H01L27/06 ,  H01L21/8258 ,  H01L29/04 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20

Abstract: An integrated semiconductor device includes a silicon body that includes single crystal silicon, a semiconductor device that is disposed within the silicon body, a III-nitride body disposed on the silicon body, and a III-nitride device that is disposed within the III-nitride body, wherein the semiconductor device is operatively coupled to the III-nitride device.

公开(公告)号：US12176813B2

公开(公告)日：2024-12-24

申请号：US17409058

申请日：2021-08-23

Applicant: Infineon Technologies Americas Corp.

Inventor： Zhiqing You ,  Tim Ng

IPC: H02M3/158 ,  G01R31/40 ,  H02M1/00

Abstract: An apparatus such as a power supply includes management hardware. The management hardware monitors operation of multiple power converter phases coupled in parallel to produce an output voltage. Based on the monitored operation, the management hardware determines a status of a series circuit path connecting windings of the multiple power converter phases. The management hardware produces status information indicating the status of the series circuit path.

公开(公告)号：US11688770B2

公开(公告)日：2023-06-27

申请号：US17457161

申请日：2021-12-01

Applicant: Infineon Technologies Americas Corp.

Inventor： Praveen Shenoy

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L21/266

CPC classification number: H01L29/0847 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/42368 ,  H01L21/266

Abstract: A method for increasing a forward biased safe operating area of a device includes forming a gate; and forming a segmented source close to the gate, wherein the segmented source includes first segments associated with a first threshold voltage and second segments associated with a second threshold voltage different from the first threshold voltage, wherein at least one device characteristic associated with the first segments is different from the same device characteristic associated with the second segments.

公开(公告)号：US20230114503A1

公开(公告)日：2023-04-13

申请号：US17496805

申请日：2021-10-08

Applicant: Infineon Technologies Americas Corp.

Inventor： Keng Chen ,  Min Chen ,  James R. Garrett ,  Danny Clavette ,  Charles P. Amirault

IPC: H02M3/158

Abstract: A power supply includes a storage component to store an output current value representative of a magnitude of output current supplied by an output voltage of a power converter to power a load. The power supply further includes an offset reference generator and a controller. The offset reference generator produces an offset reference signal, the output current value being offset by the offset reference signal. The controller controls generation of the output voltage of the power converter as a function of the offset output current value with respect to a threshold signal (value). Additionally, the controller is configured to detect a startup mode of a power converter operative to convert an input voltage into an output voltage. During the startup mode, the controller: i) produces a threshold signal having a magnitude that varies over time, and ii) controls operation of switches in the power converter as a function of the threshold signal while the power converter is operated in a diode emulation mode. Implementation of the startup mode monotonically increases a magnitude of the output voltage without dips.

公开(公告)号：US20210287952A1

公开(公告)日：2021-09-16

申请号：US16816823

申请日：2020-03-12

Applicant: Infineon Technologies Americas Corp.

Inventor： Shunhe Xiong

IPC: H01L23/15 ,  H01L23/482 ,  H01L23/29 ,  H01L23/04 ,  H01L23/00

Abstract: A packaged power device includes a ceramic package body having a top drain pad having a first area, a top source pad having a second area smaller than the first area, and a top gate pad having a third area smaller than the second area; a power device having a bottom surface affixed to a top drain pad, a die source pad coupled to the top source pad, and a die gate pad coupled to the top gate pad; and a ceramic lid affixed to the ceramic package body to form the packaged power device.

公开(公告)号：US10707160B2

公开(公告)日：2020-07-07

申请号：US15817712

申请日：2017-11-20

Applicant: Infineon Technologies Americas Corp.

Inventor： Robert T. Carroll

IPC: H01L23/498 ,  H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L21/768 ,  H01L23/482 ,  H01L23/50 ,  H01L27/06 ,  H01L29/423 ,  H02M3/335 ,  H01L27/088 ,  H02M3/158

Abstract: According to example configurations herein, an apparatus comprises a die and a host substrate. The die can include a first transistor and a second transistor. A surface of the die includes multiple conductive elements disposed thereon. The multiple conductive elements on the surface are electrically coupled to respective nodes of the first transistor and the second transistor. Prior to assembly, the first transistor and second transistor are electrically isolated from each other. During assembly, the surface of the die including the respective conductive elements is mounted on a facing of the host substrate. Accordingly, a die including multiple independent transistors can be flipped and mounted to a respective host substrate such as printed circuit board, lead frame, etc.

公开(公告)号：US10666140B2

公开(公告)日：2020-05-26

申请号：US15243242

申请日：2016-08-22

Applicant: Infineon Technologies Americas Corp.

Inventor： Eung San Cho

IPC: H02M3/158 ,  H03K7/08 ,  H02M7/537

Abstract: In some examples, a device comprises an integrated circuit comprising a first transistor and a second transistor. The device further comprises an inductor comprising a first inductor terminal and a second inductor terminal, wherein the first inductor terminal is electrically connected to the first transistor and the second transistor. The device further comprises at least five electrical connections on a first side of the device.

公开(公告)号：US10438876B2

公开(公告)日：2019-10-08

申请号：US15496951

申请日：2017-04-25

Applicant: Infineon Technologies Americas Corp.

Inventor： Dean Fernando ,  Roel Barbosa ,  Toshio Takahashi

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/31

Abstract: According to an exemplary implementation, a power quad flat no-lead (PQFN) package includes a driver integrated circuit (IC) situated on a leadframe. The PQFN package further includes low-side U-phase, low-side V-phase, and low-side W-phase power switches situated on the leadframe. A logic ground of the leadframe is coupled to a support logic circuit of the driver IC. A power stage ground of the leadframe is coupled to sources of the low-side U-phase, low-side V-phase, and low-side W-phase power switches. The power stage ground can further be coupled to gate drivers of the driver IC.

公开(公告)号：US20190124773A1

公开(公告)日：2019-04-25

申请号：US16224578

申请日：2018-12-18

Applicant: Infineon Technologies Austria AG

Inventor： Eung San Cho ,  Danny Clavette ,  Darryl Galipeau

IPC: H05K3/00 ,  H05K1/11 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46 ,  H05K1/18 ,  H05K1/14 ,  H01L23/00 ,  H01L23/538

Abstract: In one example, a method includes drilling a cavity into each contact pad of one or more contact pads of a first printed circuit board to form one or more cavities. The first printed circuit board includes an embedded integrated circuit and one or more metal layers. The method further includes forming one or more first metal layers for a second printed circuit board below a bottom surface of the first printed circuit board. The method further includes forming an electrically conductive material in the one or more cavities. The electrically conductive material electrically couples the one or more contact pads of the first printed circuit board to the second printed circuit board. The method further includes forming one or more second metal layers for the second printed circuit board above a top surface of the first printed circuit board.

公开(公告)号：US10205380B2

公开(公告)日：2019-02-12

申请号：US15431038

申请日：2017-02-13

Applicant: Infineon Technologies Americas Corp.

Inventor： Thomas J. Ribarich ,  Jorge Cerezo ,  Ajit Dubhashi

IPC: H02M7/155 ,  H02M1/32 ,  H05B6/06 ,  H05B6/12 ,  H02M1/08 ,  H02M1/44 ,  H02M7/06 ,  H02M1/00

Abstract: In one implementation, a power converter with over-voltage protection includes a power switch coupled to a power supply through a tank circuit, and a control circuit coupled to a gate of the power switch. The control circuit is configured to turn the power switch OFF based on a current from the tank circuit, thereby providing the over-voltage protection to the power converter. In one implementation, the power converter is a class-E power converter. In one implementation, the control circuit is configured to sense the current from the tank circuit based on a voltage drop across a sense resistor coupled to the power switch.