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    Dielets on flexible and stretchable packaging for microelectronics
    1.
    发明授权
    Dielets on flexible and stretchable packaging for microelectronics 有权

    公开(公告)号：US11355443B2

    公开(公告)日：2022-06-07

    申请号：US16515417

    申请日：2019-07-18

    申请人： Invensas Corporation

    发明人： Shaowu Huang ,  Javier A. Delacruz

    IPC分类号： H01L23/538 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L25/065

    摘要： Dielets on flexible and stretchable packaging for microelectronics are provided. Configurations of flexible, stretchable, and twistable microelectronic packages are achieved by rendering chip layouts, including processors and memories, in distributed collections of dielets implemented on flexible and/or stretchable media. High-density communication between the dielets is achieved with various direct-bonding or hybrid bonding techniques that achieve high conductor count and very fine pitch on flexible substrates. An example process uses high-density interconnects direct-bonded or hybrid bonded between standard interfaces of dielets to create a flexible microelectronics package. In another example, a process uses high-density interconnections direct-bonded between native interconnects of the dielets to create the flexible microelectronics packages, without the standard interfaces.

    Symbiotic Network On Layers
    2.
    发明申请
    Symbiotic Network On Layers 有权

    公开(公告)号：US20220150184A1

    公开(公告)日：2022-05-12

    申请号：US17583872

    申请日：2022-01-25

    申请人： Invensas Corporation

    发明人： Javier A. DeLaCruz ,  Belgacem Haba ,  Rajesh Katkar

    IPC分类号： H04L49/109

    摘要： The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

    Apparatus For Non-Volatile Random Access Memory Stacks
    4.
    发明申请
    Apparatus For Non-Volatile Random Access Memory Stacks 有权

    公开(公告)号：US20210193624A1

    公开(公告)日：2021-06-24

    申请号：US17122149

    申请日：2020-12-15

    申请人： Invensas Corporation

    发明人： Javier A. Delacruz ,  Belgacem Haba ,  Rajesh Katkar ,  Pearl Po-Yee Cheng

    IPC分类号： H01L25/065 ,  H01L25/18 ,  H01L23/00

    摘要： A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.

    Non-Volatile Dynamic Random Access Memory
    5.
    发明申请
    Non-Volatile Dynamic Random Access Memory 有权

    公开(公告)号：US20210118864A1

    公开(公告)日：2021-04-22

    申请号：US17070253

    申请日：2020-10-14

    申请人： Invensas Corporation

    发明人： Javier A. Delacruz ,  Pearl Po-Yee Cheng ,  David Edward Fisch

    IPC分类号： H01L25/18 ,  H01L25/065 ,  H01L23/00

    摘要： The present disclosure provides for a stacked memory combining RAM and one or more layers of NVM, such as NAND. For example, a first layer of RAM, such as DRAM, is coupled to multiple consecutive layers of NAND using direct bonding interconnect (DBI®). Serialization and overhead that exists in periphery of the NVM may be stripped to manage the data stored therein. The resulting connections between the RAM and the NVM are high bandwidth, high pincount interconnects. Interconnects between each of the one or more layers of NVM are also very dense.

    Tall and fine pitch interconnects
    7.
    发明授权
    Tall and fine pitch interconnects 有权

    公开(公告)号：US10818629B2

    公开(公告)日：2020-10-27

    申请号：US16127696

    申请日：2018-09-11

    申请人： Invensas Corporation

    发明人： Cyprian Emeka Uzoh ,  Rajesh Katkar

    IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/00 ,  H01L21/683 ,  H01L25/065 ,  H05K3/34

    摘要： Representative implementations of devices and techniques provide interconnect structures and components for coupling various carriers, printed circuit board (PCB) components, integrated circuit (IC) dice, and the like, using tall and/or fine pitch physical connections. Multiple layers of conductive structures or materials are arranged to form the interconnect structures and components. Nonwettable barriers may be used with one or more of the layers to form a shape, including a pitch of one or more of the layers.