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    Profile engineered, electrically active thin film devices
    1.
    发明授权
    Profile engineered, electrically active thin film devices 有权
    型材设计，电活性薄膜器件

    公开(公告)号：US08426905B2

    公开(公告)日：2013-04-23

    申请号：US12243880

    申请日：2008-10-01

    申请人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    发明人： Arvind Kamath ,  Erik Scher ,  Patrick Smith ,  Aditi Chandra ,  Steven Molesa

    IPC分类号： H01L29/788

    CPC分类号： H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

    摘要： The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

    摘要翻译： 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

    Polysilane compositions, methods for their synthesis and films formed therefrom
    3.
    发明授权
    Polysilane compositions, methods for their synthesis and films formed therefrom 有权
    聚硅烷组合物，其合成方法和由其形成的薄膜

    公开(公告)号：US08057865B1

    公开(公告)日：2011-11-15

    申请号：US11893140

    申请日：2007-08-14

    申请人： Wenzhuo Guo ,  Vladimir K. Dioumaev ,  Joerg Rockenberger ,  Brent Ridley

    发明人： Wenzhuo Guo ,  Vladimir K. Dioumaev ,  Joerg Rockenberger ,  Brent Ridley

    IPC分类号： C08F2/48 ,  C08J7/18 ,  B05D3/02 ,  B05D3/06

    CPC分类号： C07F7/0896 ,  C08G77/60 ,  C08L83/16

    摘要： Polysilanes, inks containing the same, and methods for their preparation are disclosed. The polysilane generally has the formula H—[(AHR)n(c—AmHpm−2)q]—H, where each instance of A is independently Si or Ge; R is H, —AaHa+1Ra, Halogen, aryl or substituted aryl; (n+a)≧10 if q=0, q≧3 if n=0, and (n+q)≧6 if both n and q≠0; p is 1 or 2; and m is from 3 to 12. In one aspect, the method generally includes the steps of combining a silane compound of the formula AHaR14−a, the formula AkHgR1′h and/or the formula c—AmHpmR1rm with a catalyst of the formula R4xR5yMXz (or an immobilized derivative thereof) to form a poly(aryl)silane; then washing the poly(aryl)silane with an aqueous washing composition and contacting the poly(aryl)silane with an adsorbent to remove the metal M. In another aspect, the method includes the steps of halogenating a polyarylsilane to form a halopolysilane; and reducing the halopolysilane with a metal hydride to form the polysilane. The synthesis of semiconductor inks via dehydrocoupling of silanes and/or germanes allows for tuning of the ink properties (e.g., viscosity, boiling point, and surface tension) and for deposition of silicon films or islands by spincoating, inkjetting, dropcasting, etc., with or without the use of UV irradiation.

    摘要翻译： 公开了聚硅烷，含有它们的油墨及其制备方法。 聚硅烷通常具有式H - [（AHR）n（c-AmHpm-2）q] -H，其中A的每个实例独立地为Si或Ge; R为H，-AaHa + 1Ra，卤素，芳基或取代的芳基; （n + a）≥10，如果n = 0，则q≥3，如果n和q≠0，则（n + q）≥6; p为1或2; 一方面，该方法通常包括将式AHaR14-a，式AkHgR1'h和/或式c-AmHpmR1rm的硅烷化合物与式R4xR5yMXz的催化剂组合的步骤 （或其固定化的衍生物）以形成聚（芳基）硅烷; 然后用水性洗涤组合物洗涤聚（芳基）硅烷，并使聚（芳基）硅烷与吸附剂接触以除去金属M.另一方面，该方法包括卤化聚芳基硅烷以形成卤代聚硅烷的步骤; 并用金属氢化物还原卤代聚硅烷以形成聚硅烷。 通过硅烷和/或锗烷的脱氢耦合来合成半导体油墨允许调节油墨性能（例如粘度，沸点和表面张力）以及通过旋涂，喷墨，滴浇等沉积硅膜或岛， 有或没有使用紫外线照射。

    Multi-mode tags and methods of making and using the same
    4.
    发明授权
    Multi-mode tags and methods of making and using the same 失效
    多模式标签及其制作和使用方法

    公开(公告)号：US07750792B2

    公开(公告)日：2010-07-06

    申请号：US11870775

    申请日：2007-10-11

    申请人： Patrick Smith ,  James Montague Cleeves ,  Vikram Pavate ,  Vivek Subramanian

    发明人： Patrick Smith ,  James Montague Cleeves ,  Vikram Pavate ,  Vivek Subramanian

    IPC分类号： H04Q5/22

    CPC分类号： G06K19/0707 ,  G06K19/0712 ,  G06K19/0723 ,  G08B13/2448 ,  H04W88/06 ,  Y02D70/166

    摘要： Multi-mode (e.g., EAS and RFID) tags and methods for making and using the same are disclosed. The tag generally includes an antenna, an electronic article surveillance (EAS) function block coupled to the antenna, and one or more identification function blocks coupled to the antenna in parallel with the EAS function block. The method of reading the tag generally includes the steps of applying an electric field to the tag, detecting the tag when the electric field has a relatively low power, and detecting an identification signal from the tag when the electric field has a relatively high power. The present invention advantageously enables a single tag to be used for both inventory and anti-theft purposes, thereby improving inventory management and control at reduced system and/or “per-article” costs.

    摘要翻译： 公开了多模式（例如，EAS和RFID）标签及其制造和使用方法。 标签通常包括耦合到天线的天线，电子物品监视（EAS）功能块以及与EAS功能块并行耦合到天线的一个或多个识别功能块。 读取标签的方法通常包括对标签施加电场的步骤，当电场具有相对低的功率时检测标签，以及当电场具有相对高的功率时，从标签中检测识别信号。 本发明有利地使单个标签用于库存和防盗目的，从而改进库存管理和减少系统和/或“每件物品”成本的控制。

    Semiconductor device and methods for making the same
    5.
    发明授权
    Semiconductor device and methods for making the same 有权
    半导体器件及其制造方法

    公开(公告)号：US07691691B1

    公开(公告)日：2010-04-06

    申请号：US11805620

    申请日：2007-05-23

    申请人： James Montague Cleeves

    发明人： James Montague Cleeves

    IPC分类号： H01L21/00

    CPC分类号： H01L29/78621 ,  H01L29/66757

    摘要： Thin film transistors (TFT) and methods for making same. The TFTs generally comprise: (a) a semiconductor layer comprising source and drain terminals and a channel region therebetween; (b) a gate electrode comprising a gate and a gate dielectric layer between the gate and the channel region; (c) a first dielectric layer adjacent to the gate electrode and in contact with the source and drain terminals, the first dielectric layer comprising a material which comprises a dopant therein; and (d) an electrically functional source/drain extensions in the channel region, adjacent to the source and drain terminals, comprising a material which comprises the same dopant as the first dielectric layer.

    摘要翻译： 薄膜晶体管（TFT）及其制造方法。 TFT通常包括：（a）包括源极和漏极端子以及它们之间的沟道区域的半导体层; （b）栅电极，在栅极和沟道区之间包括栅极和栅介质层; （c）与栅电极相邻并与源极和漏极端子接触的第一电介质层，第一介电层包括在其中包含掺杂剂的材料; 和（d）沟道区域中的与源极和漏极端子相邻的电功率源极/漏极延伸部分，包括与第一介电层相同的掺杂剂的材料。

    MOS transistor with self-aligned source and drain, and method for making the same
    6.
    发明授权
    MOS transistor with self-aligned source and drain, and method for making the same 失效
    具有自对准源极和漏极的MOS晶体管及其制造方法

    公开(公告)号：US07619248B1

    公开(公告)日：2009-11-17

    申请号：US11084448

    申请日：2005-03-18

    申请人： James Montague Cleeves

    发明人： James Montague Cleeves

    IPC分类号： H01L31/00

    CPC分类号： H01L29/78618 ,  H01L29/04 ,  H01L29/66757

    摘要： A MOS transistor with self-aligned source/drain terminals, and methods for its manufacture. The transistor generally includes an electrically functional substrate, a dielectric film on portions of the substrate, a gate on the dielectric film, and polycrystalline source and drain terminals self-aligned with the gate. The method generally includes forming an amorphous semiconductor material on a gate and on exposed portions of an electrically functional substrate, irradiating an upper surface of the amorphous semiconductor material to form self-aligned polycrystalline semiconducting source/drain terminal layers, and (optionally) selectively removing the non-irradiated amorphous semiconductor material portions. The present invention advantageously provides MOS thin film transistors having reliable electrical characteristics quickly, efficiently, and/or at a low cost by eliminating one or more conventional photolithographic steps.

    摘要翻译： 具有自对准源极/漏极端子的MOS晶体管及其制造方法。 晶体管通常包括电功能衬底，在衬底的部分上的电介质膜，电介质膜上的栅极，以及与栅极自对准的多晶源极和漏极端子。 该方法通常包括在栅极上和在电功能基板的暴露部分上形成非晶半导体材料，照射非晶半导体材料的上表面以形成自对准多晶半导体源极/漏极端子层，和（可选地）选择性地去除 未照射的非晶半导体材料部分。 本发明有利地通过消除一个或多个常规光刻步骤来快速，有效地和/或以低成本提供具有可靠电特性的MOS薄膜晶体管。

    Methods of forming a doped semiconductor thin film, doped semiconductor thin film structures, doped silane compositions, and methods of making such compositions
    7.
    发明授权
    Methods of forming a doped semiconductor thin film, doped semiconductor thin film structures, doped silane compositions, and methods of making such compositions 有权
    形成掺杂半导体薄膜，掺杂半导体薄膜结构，掺杂硅烷组合物的方法和制备这种组合物的方法

    公开(公告)号：US07314513B1

    公开(公告)日：2008-01-01

    申请号：US10949013

    申请日：2004-09-24

    申请人： Fabio Zürcher ,  Wenzhuo Guo ,  Joerg Rockenberger ,  Vladimir K. Dioumaev ,  Brent Ridley ,  Klaus Kunze ,  James Montague Cleeves

    发明人： Fabio Zürcher ,  Wenzhuo Guo ,  Joerg Rockenberger ,  Vladimir K. Dioumaev ,  Brent Ridley ,  Klaus Kunze ,  James Montague Cleeves

    IPC分类号： C09D183/16

    CPC分类号： H01L21/02576 ,  H01L21/02532 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02628

    摘要： Methods for forming doped silane and/or semiconductor thin films, doped liquid phase silane compositions useful in such methods, and doped semiconductor thin films and structures. The composition is generally liquid at ambient temperatures and includes a Group IVA atom source and a dopant source. By irradiating a doped liquid silane during at least part of its deposition, a thin, substantially uniform doped oligomerized/polymerized silane film may be formed on a substrate. Such irradiation is believed to convert the doped silane film into a relatively high-molecular weight species with relatively high viscosity and relatively low volatility, typically by cross-linking, isomerization, oligomerization and/or polymerization. A film formed by the irradiation of doped liquid silanes can later be converted (generally by heating and annealing/recrystallization) into a doped, hydrogenated, amorphous silicon film or a doped, at least partially polycrystalline silicon film suitable for electronic devices. Thus, the present invention enables use of high throughput, low cost equipment and techniques for making doped semiconductor films of commercial quality and quantity from doped “liquid silicon.”

    摘要翻译： 用于形成掺杂的硅烷和/或半导体薄膜的方法，用于这种方法的掺杂的液相硅烷组合物，以及掺杂的半导体薄膜和结构。 组合物在环境温度下通常是液体，并且包括IVA族原子源和掺杂剂源。 通过在其沉积的至少一部分期间照射掺杂的液体硅烷，可以在衬底上形成薄的，基本上均匀的掺杂的低聚/聚合的硅烷膜。 据信这种照射将掺杂的硅烷膜转化成相对高分子量的物质，具有相对较高的粘度和较低挥发性，通常通过交联，异构化，低聚和/或聚合。 通过掺杂的液体硅烷的照射形成的膜可以随后通过加热和退火/重结晶转化成掺杂的，氢化的非晶硅膜或适用于电子器件的掺杂的至少部分多晶的硅膜。 因此，本发明能够使用高通量，低成本的设备和技术来制造掺杂的“液态硅”具有商业质量和数量的掺杂半导体膜。

    Electronic article surveillance (EAS) tag/device with coplanar and/or multiple coil circuits, an EAS tag/device with two or more memory bits, and methods for tuning the resonant frequency of an RLC EAS tag/device
    8.
    发明授权
    Electronic article surveillance (EAS) tag/device with coplanar and/or multiple coil circuits, an EAS tag/device with two or more memory bits, and methods for tuning the resonant frequency of an RLC EAS tag/device 失效
    具有共面和/或多个线圈电路的电子物品监视（EAS）标签/设备，具有两个或多个存储位的EAS标签/设备以及用于调谐RLC EAS标签/设备的谐振频率的方法

    公开(公告)号：US07286053B1

    公开(公告)日：2007-10-23

    申请号：US11104375

    申请日：2005-04-11

    申请人： Christopher Gudeman ,  J. Devin MacKenzie ,  J. Montague Cleeves ,  Jose Arreola

    发明人： Christopher Gudeman ,  J. Devin MacKenzie ,  J. Montague Cleeves ,  Jose Arreola

    IPC分类号： G08B13/14

    CPC分类号： G08B13/242 ,  G08B13/2414 ,  G08B13/2417 ,  G08B13/2437 ,  G08B13/2448

    摘要： An electronic article surveillance (EAS) tag/device with coplanar and/or multiple coil circuits, a tag/device with two or more memory bits, and methods for making and tuning the resonant frequency of an EAS tag/device. The device generally includes: an outer inductor having one end coupled to a capacitor plate; an inner inductor having one end coupled to an other capacitor plate; a first dielectric film on the outer and inner inductors and the capacitor plates coupled thereto, having openings therein exposing other ends of the outer and inner inductors; a linear capacitor plate and a nonlinear capacitor plate on the first dielectric film; a second dielectric film containing holes therein for the second linear and nonlinear capacitor plates, and exposing the other ends of the first and second inductors; and first and second conducting straps on the second dielectric film, electrically connecting one of the exposed inductor ends to a corresponding second capacitor plate.

    摘要翻译： 具有共面和/或多个线圈电路的电子物品监视（EAS）标签/设备，具有两个或多个存储器位的标签/设备，以及用于制造和调谐EAS标签/设备的谐振频率的方法。 器件通常包括：外部电感器，其一端耦合到电容器板; 内部电感器，其一端耦合到另一个电容器板; 外电感器和内电感器上的第一电介质膜和耦合到其上的电容器板，其中具有开口的外部和内部电感器的另一端; 第一电介质膜上的线性电容器板和非线性电容器板; 第二电介质膜，用于所述第二线性和非线性电容器板，并且暴露所述第一和第二电感器的另一端; 以及在第二介电膜上的第一和第二导电带，将暴露的电感器端中的一个电连接到相应的第二电容器板。