公开(公告)号：US08404586B2

公开(公告)日：2013-03-26

申请号：US11635044

申请日：2006-12-07

申请人： Kazumasa Tanida ,  Mitsuo Umemoto ,  Yukiharu Akiyama

发明人： Kazumasa Tanida ,  Mitsuo Umemoto ,  Yukiharu Akiyama

IPC分类号： H01L21/44

CPC分类号： H01L25/0657 ,  H01L23/481 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13144 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73207 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/04941 ,  H01L2924/12041 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

摘要： A manufacturing method for a semiconductor device includes: the step of preparing a semiconductor chip which is provided with a functional element formed on a front surface side of a semiconductor substrate, a feedthrough electrode which is placed within a through hole that penetrates the semiconductor substrate, a front surface side connection member which protrudes from the front surface, and a rear surface side connection member which has a joining surface within a recess that is formed in a rear surface; the step of preparing a solid state device where a solid state device side connection member for connection to the front surface side connection member is formed on one surface; and the joining step of making the front surface of the semiconductor chip face the first surface of the solid state device by holding the rear surface of the semiconductor chip, and of joining the front surface side connection member to the solid state device side connection member.

摘要翻译： 半导体装置的制造方法包括：准备半导体芯片的步骤，该半导体芯片设置有形成在半导体基板的正面侧的功能元件，放置在贯通半导体基板的通孔内的馈通电极， 从前表面突出的前表面侧连接构件和在形成在后表面的凹部内具有接合表面的后表面侧连接构件; 制备固态器件的步骤，其中在一个表面上形成用于连接到前表面侧连接部件的固态器件侧连接部件; 并且通过保持半导体芯片的后表面并将前表面侧连接构件接合到固态器件侧连接构件，使半导体芯片的前表面面向固态器件的第一表面的接合步骤。

公开(公告)号：US08387113B2

公开(公告)日：2013-02-26

申请号：US12298774

申请日：2007-05-10

申请人： Hidetoshi Shimada ,  Norio Fujimori ,  Keiichi Komaki ,  Keisuke Koide ,  Tsuyoshi Ookubo ,  Kenichiro Kamijo ,  Daiki Yokoyama ,  Kenichi Takahira ,  Katsuhisa Tatsukawa

发明人： Hidetoshi Shimada ,  Norio Fujimori ,  Keiichi Komaki ,  Keisuke Koide ,  Tsuyoshi Ookubo ,  Kenichiro Kamijo ,  Daiki Yokoyama ,  Kenichi Takahira ,  Katsuhisa Tatsukawa

IPC分类号： G06F7/04

CPC分类号： G06F21/71 ,  G06F1/28 ,  G06F21/40 ,  G06F21/42 ,  G06F21/44 ,  G06F21/81 ,  G06F21/85 ,  G06F2221/2103 ,  G06F2221/2129 ,  G06F2221/2153

摘要： An authenticating system according to the present invention has a characteristic structure of which an authenticating section 32 of a note type PC 10 and an authenticating section 42 of a battery 20 are directly connected through I/O ports 51 and 61, respectively. Thus, the authenticating system according to the present invention can be relatively easily accomplished using a conventional system. The present invention can be applied to a system that is composed of a plurality of electronic devices that perform an authenticating process.

摘要翻译： 根据本发明的认证系统具有以下特征结构：便携式PC10的认证部分32和电池20的认证部分42分别通过I / O端口51和61直接连接。 因此，根据本发明的认证系统可以使用常规系统相对容易地实现。 本发明可以应用于由执行认证处理的多个电子设备组成的系统。

公开(公告)号：US20110242120A1

公开(公告)日：2011-10-06

申请号：US12750773

申请日：2010-03-31

申请人： Akihito AKAI ,  Yoshiki Kurokawa ,  Goki Toshima

发明人： Akihito AKAI ,  Yoshiki Kurokawa ,  Goki Toshima

IPC分类号： G06F13/00

CPC分类号： G09G3/3406 ,  G09G2320/0646 ,  G09G2360/16

摘要： The display unit can reduce the electric power consumed by the process of calculating an adjustment coefficient for display data, as typified by gradient control, and it can be readily adapted even to a display panel with a higher resolution. The display unit includes: a plurality of driving units arrayed in parallel and each operable to output a drive signal to a display panel; a plurality of first calculation units, and a plurality of display RAMs, each paired with one first calculation unit, the pairs of the first calculation units and display RAMs laid out along a direction of the parallel array of the driving units; and a second calculation unit which distributes display data supplied from outside to the display RAMs, receives display data from the display RAMs in parallel to analyze a histogram of tone distribution of pixel data corresponding to one screen, and calculates the adjustment coefficient based on a result of the analysis. In the display unit, the adjustment coefficient thus calculated is sent back to the first calculation units. The first calculation unit performs a calculation using display data read from the corresponding display RAM and the adjustment coefficient thereby to create drive data for the display panel.

摘要翻译： 显示单元可以通过梯度控制代表的计算显示数据的调整系数的处理来减少消耗的电力，并且可以容易地适应于具有更高分辨率的显示面板。 显示单元包括：并行排列的多个驱动单元，每个驱动单元可操作以将驱动信号输出到显示面板; 多个第一计算单元和多个显示RAM，每个显示RAM与一个第一计算单元配对，沿着驱动单元的并行阵列的方向布置的第一计算单元和显示RAM对; 以及第二计算单元，其将从外部提供的显示数据分配到显示RAM，并行地从显示RAM接收显示数据，以分析与一个屏幕相对应的像素数据的色调分布的直方图，并且基于结果计算调整系数 的分析。 在显示单元中，将如此计算的调整系数发送回第一计算单元。 第一计算单元使用从对应的显示RAM读取的显示数据和调整系数进行计算，从而创建显示面板的驱动数据。

公开(公告)号：US20110207312A1

公开(公告)日：2011-08-25

申请号：US13103558

申请日：2011-05-09

申请人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

发明人： Hirokazu Sayama ,  Kazunobu Ohta ,  Hidekazu Oda ,  Kouhei Sugihara

IPC分类号： H01L21/283

CPC分类号： H01L29/7845 ,  H01L21/26506 ,  H01L21/32155 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823443 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/10805 ,  H01L27/10844 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/4925 ,  H01L29/4933 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/7842 ,  H01L29/7848

摘要： A gate insulating film (13) and a gate electrode (14) of non-single crystalline silicon for forming an nMOS transistor are provided on a silicon substrate (10). Using the gate electrode (14) as a mask, n-type dopants having a relatively large mass number (70 or more) such as As ions or Sb ions are implanted, to form a source/drain region of the nMOS transistor, whereby the gate electrode (14) is amorphized. Subsequently, a silicon oxide film (40) is provided to cover the gate electrode (14), at a temperature which is less than the one at which recrystallization of the gate electrode (14) occurs. Thereafter, thermal processing is performed at a temperature of about 1000° C., whereby high compressive residual stress is exerted on the gate electrode (14), and high tensile stress is applied to a channel region under the gate electrode (14). As a result, carrier mobility of the nMOS transistor is enhanced.

摘要翻译： 在硅衬底（10）上设置用于形成nMOS晶体管的非单晶硅的栅极绝缘膜（13）和栅电极（14）。 使用栅极（14）作为掩模，注入具有相对较大质量数（70以上）的诸如As离子或Sb离子的n型掺杂剂，以形成nMOS晶体管的源极/漏极区域，由此， 栅电极（14）非晶化。 随后，提供氧化硅膜（40）以比栅电极（14）再结晶发生的温度小的温度覆盖栅电极（14）。 此后，在约1000℃的温度下进行热处理，由此在栅电极（14）上施加高的压缩残余应力，并且对栅电极（14）下的沟道区域施加高的拉伸应力。 结果，增强了nMOS晶体管的载流子迁移率。

公开(公告)号：US07960076B2

公开(公告)日：2011-06-14

申请号：US12329126

申请日：2008-12-05

申请人： Takashi Kamo ,  Osamu Suga ,  Toshihiko Tanaka

发明人： Takashi Kamo ,  Osamu Suga ,  Toshihiko Tanaka

IPC分类号： G03F1/00

CPC分类号： G03F1/24 ,  B82Y10/00 ,  B82Y40/00 ,  G03F1/58

摘要： A reflective-type mask having a main surface including a pattern region in the main surface, the pattern region including a multilayer reflective film which reflects the exposure light and a first absorber pattern on the multilayer reflective film, the first absorber pattern including a pattern which absorbs the exposure light and corresponds to a pattern to be formed on a wafer, a light shielding region in the main surface for preventing a region on the wafer excluding a predetermined region from being irradiated with the exposure light when the main surface is irradiated with the exposure light for transferring the first absorber pattern to the predetermined region, the light shielding region including a second absorber pattern having a lower reflectivity to the exposure light than the first absorber pattern and being provided in a position differing from a position in which the first absorber pattern is provided.

摘要翻译： 一种反射型掩模，其具有包括主表面中的图案区域的主表面，所述图案区域包括反射所述曝光光的多层反射膜和所述多层反射膜上的第一吸收体图案，所述第一吸收体图案包括图案， 吸收曝光光并且对应于要在晶片上形成的图案，主表面上的遮光区域，用于防止当主表面被照射时，除了预定区域之外的晶片上的区域被照射曝光 用于将第一吸收体图案转印到预定区域的曝光光，所述遮光区域包括与所述第一吸收体图案相比对所述曝光光具有较低反射率的第二吸收体图案，并且设置在与所述第一吸收体 提供图案。

公开(公告)号：US20110090605A1

公开(公告)日：2011-04-21

申请号：US12977624

申请日：2010-12-23

申请人： Takayasu ITO ,  Mitsuru Hiraki ,  Koichi Ashiga

发明人： Takayasu ITO ,  Mitsuru Hiraki ,  Koichi Ashiga

IPC分类号： H02H3/20

CPC分类号： H01L23/50 ,  H01L23/60 ,  H01L24/06 ,  H01L27/0207 ,  H01L27/0266 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2924/01029 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H02M3/00 ,  H02M3/07 ,  H02M3/157 ,  H01L2924/00

摘要： An integrated circuit formed on a semiconductor chip includes voltage regulators for stepping down an externally-supplied power voltage to produce an internal power voltage, and internal circuits which operate based on the internal power voltage. The voltage regulators are laid in the area of the buffers and protective elements for the input/output signals and power voltages so that the overhead area due to the on-chip provision of the voltage regulators is minimized. The internal power voltage is distributed to the internal circuits through a looped main power line, with an electrode pad for connecting an external capacitor for stabilizing the internal power voltage being provided on it, so that the internal power voltage is stabilized and the power consumption of the integrated circuit is minimized.

摘要翻译： 形成在半导体芯片上的集成电路包括用于降低外部提供的电源电压以产生内部电源电压的电压调节器，以及基于内部电源电压工作的内部电路。 电压调节器被放置在缓冲器和保护元件的区域中用于输入/输出信号和电源电压，使得由于电压调节器的片上提供而导致的开销面积被最小化。 内部电源电压通过环形主电源线分配到内部电路，电极焊盘用于连接外部电容器，用于稳定其上提供的内部电源电压，从而内部电源电压稳定，功耗 集成电路最小化。

公开(公告)号：US07926010B2

公开(公告)日：2011-04-12

申请号：US12131582

申请日：2008-06-02

申请人： Shogo Narukawa ,  Yoshikazu Nagamura

发明人： Shogo Narukawa ,  Yoshikazu Nagamura

IPC分类号： G06F17/50

CPC分类号： G03F1/84

摘要： A method of determining defects in photomasks according to the present invention is designed to increase the yield of the manufacture of photomasks and to decrease the cost of inspecting the photomasks. In the method, circuit data 1 representing a circuit to be formed on a semiconductor substrate by photolithography is prepared, and layout data 2 is prepared from the circuit data 1. The layout data is converted to compensated layout data by performing RET. Further, mask-manufacturing data is developed from the compensated layout data. To form patterns on a semiconductor substrate by photolithography, attribute information is imparted to the mask-manufacturing data. The attribute information represents whether the patterns are adaptive to electrically active regions or electrically non-active region. In the mask-inspecting process 6, a criterion for determining whether the patterns formed on the photomasks have defects is changed in accordance with the attribute information.

摘要翻译： 根据本发明的确定光掩模中的缺陷的方法被设计为增加光掩模的制造的产量并降低检查光掩模的成本。 在该方法中，准备表示通过光刻形成在半导体衬底上的电路的电路数据1，并从电路数据1准备布局数据2.通过执行RET将布局数据转换为补偿布局数据。 此外，从补偿的布局数据开发掩模制造数据。 为了通过光刻法在半导体衬底上形成图案，赋予掩模制造数据赋予属性信息。 属性信息表示图案是否适应于电活性区域或电非活性区域。 在掩模检查过程6中，根据属性信息改变用于确定形成在光掩模上的图案是否具有缺陷的标准。

公开(公告)号：US07911855B2

公开(公告)日：2011-03-22

申请号：US12280074

申请日：2007-02-22

申请人： Akira Tada

发明人： Akira Tada

IPC分类号： G11C7/00

CPC分类号： G06F1/32 ,  H03K19/0016 ,  H04W52/0261

摘要： A semiconductor device capable of reducing power consumption is provided. When a power to an internal circuit is interrupted, e.g., in a standby mode, a switch is turned off, and a pseudo-ground line is charged with a leak current of the internal circuit to raise a potential thereof. After the switch is turned off, a switch connected to a charge supply unit is turned on while the potential is rising, so that the charge supply unit is electrically coupled to the pseudo-ground line. Thereby, charges accumulated in the charge supply unit are discharged to the pseudo-ground line. The switch is turned off to decouple electrically the charge supply unit from the pseudo-ground line. Thereby, when the power supply is interrupted, a part of the charges for raising the potential of the pseudo-ground line is supplemented with the charges of the charge supply unit.

摘要翻译： 提供能够降低功耗的半导体器件。 当内部电路的电源被中断时，例如在待机模式中，开关被断开，并且伪地线用内部电路的漏电流充电以提高其电位。 在开关断开之后，连接到充电电源单元的开关在电位上升时导通，使得电荷供给单元电耦合到伪地线。 由此，蓄积在电荷供给单元中的电荷被放电到伪地线。 关闭开关以将电荷供应单元与伪接地线电连接。 因此，当电源中断时，用于提高伪地线的电位的一部分电荷用电荷供应单元的电荷补充。

公开(公告)号：US20100314676A1

公开(公告)日：2010-12-16

申请号：US12861407

申请日：2010-08-23

申请人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

发明人： Satoru Akiyama ,  Takao Watanabe ,  Yuichi Matsui ,  Masahiko Hiratani

IPC分类号： H01L27/108

CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10814 ,  H01L27/10885 ,  H01L27/10894 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A memory cell capacitor (C3) of a DRAM is formed by use of a MIM capacitor which uses as its electrode a metal wiring line of the same layer (M3) as metal wiring lines within a logic circuit (LOGIC), thereby enabling reduction of process costs. Higher integration is achievable by forming the capacitor using a high dielectric constant material and disposing it above a wiring layer in which bit lines (BL) are formed. In addition, using 2T cells makes it possible to provide a sufficient signal amount even when letting them operate with a low voltage. By commonizing the processes for fabricating capacitors in analog (ANALOG) and memory (MEM), it is possible to realize a semiconductor integrated circuit with the logic, analog and memory mounted together on one chip at low costs.

摘要翻译： DRAM的存储单元电容器（C3）通过使用MIM电容器形成，该MIM电容器使用与逻辑电路（LOGIC）内的金属布线相同层（M3）的金属布线作为其电极，从而能够减少 工艺成本 通过使用高介电常数材料形成电容器并将其布置在其中形成位线（BL）的布线层上方，可以实现更高的积分。 此外，使用2T电池使得即使当它们以低电压工作时也可以提供足够的信号量。 通过对模拟（ANALOG）和存储器（MEM）中制造电容器的工艺进行通用化，可以以低成本在一个芯片上实现将逻辑，模拟和存储器安装在一起的半导体集成电路。

公开(公告)号：US20100308858A1

公开(公告)日：2010-12-09

申请号：US12857063

申请日：2010-08-16

申请人： Hideyuki NODA ,  Kazunori Saitoh ,  Kazutami Ariomoto ,  Katsumi Dosaka

发明人： Hideyuki NODA ,  Kazunori Saitoh ,  Kazutami Ariomoto ,  Katsumi Dosaka

IPC分类号： H03K19/003

CPC分类号： G11C7/1006

摘要： A memory cell mat is divided into a plurality of entries, and an arithmetic logic unit is arranged corresponding to each entry. Between the entries and the corresponding arithmetic logic units, arithmetic/logic operation is executed in bit-serial and entry-parallel manner. Where parallel operation is not very effective, data is transferred in entry-serial and bit-parallel manner to a group of processors provided at a lower portion of the memory mat. In this manner, a large amount of data can be processed at high speed regardless of the contents of operation or data bit width.

摘要翻译： 存储单元垫被分成多个条目，并且对应于每个条目布置了算术逻辑单元。 在条目和相应的算术逻辑单元之间，以比特串行和并行方式执行算术/逻辑运算。 在并行操作不是非常有效的情况下，数据以串行和位并行方式传送到设置在存储器垫的下部的一组处理器。 以这种方式，无论操作内容或数据位宽度如何，都可以高速处理大量的数据。