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    Magnetic Element Having Low Saturation Magnetization
    2.
    发明申请
    Magnetic Element Having Low Saturation Magnetization 有权
    具有低饱和磁化的磁性元件

    公开(公告)号：US20110241141A1

    公开(公告)日：2011-10-06

    申请号：US13160438

    申请日：2011-06-14

    申请人： Hide Nagai ,  Zhitao Diao ,  Yiming Huai

    发明人： Hide Nagai ,  Zhitao Diao ,  Yiming Huai

    IPC分类号： H01L29/82

    CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1659

    摘要： A magnetic device including a magnetic element is described. The magnetic element includes a fixed layer having a fixed layer magnetization, a spacer layer that is nonmagnetic, and a free layer having a free layer magnetization. The free layer is changeable due to spin transfer when a write current above a threshold is passed through the first free layer. The free layer is includes low saturation magnetization materials.

    摘要翻译： 描述包括磁性元件的磁性装置。 磁性元件包括具有固定层磁化的固定层，非磁性的间隔层和具有自由层磁化的自由层。 当超过阈值的写入电流通过第一自由层时，由于自旋转移，自由层是可变的。 自由层包括低饱和磁化材料。

    Magnetic element having low saturation magnetization
    3.
    发明授权
    Magnetic element having low saturation magnetization 有权
    具有低饱和磁化强度的磁性元件

    公开(公告)号：US07982275B2

    公开(公告)日：2011-07-19

    申请号：US11843496

    申请日：2007-08-22

    申请人： Hide Nagai ,  Zhitao Diao ,  Yiming Huai

    发明人： Hide Nagai ,  Zhitao Diao ,  Yiming Huai

    IPC分类号： H01L29/82 ,  H01L43/00

    CPC分类号： G11C11/1675 ,  G11C11/161 ,  G11C11/1659

    摘要： A magnetic device including a magnetic element is described. The magnetic element includes a fixed layer having a fixed layer magnetization, a spacer layer that is nonmagnetic, and a free layer having a free layer magnetization. The free layer is changeable due to spin transfer when a write current above a threshold is passed through the first free layer. The free layer is includes low saturation magnetization materials.

    摘要翻译： 描述包括磁性元件的磁性装置。 磁性元件包括具有固定层磁化的固定层，非磁性的间隔层和具有自由层磁化的自由层。 当超过阈值的写入电流通过第一自由层时，由于自旋转移，自由层是可变的。 自由层包括低饱和磁化材料。

    SWITCHING POWER SUPPLY DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND POWER SUPPLY DEVICE
    4.
    发明申请
    SWITCHING POWER SUPPLY DEVICE, SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND POWER SUPPLY DEVICE 有权
    切换电源装置，半导体集成电路装置和电源装置

    公开(公告)号：US20110062927A1

    公开(公告)日：2011-03-17

    申请号：US12950222

    申请日：2010-11-19

    申请人： Toshio NAGASAWA ,  Ryotaro KUDO

    发明人： Toshio NAGASAWA ,  Ryotaro KUDO

    IPC分类号： G05F1/00

    CPC分类号： H02M3/156 ,  Y10T307/826

    摘要： A switching power supply device performs a stable operation with fast response for a semiconductor integrated circuit device. A capacitor is provided between the output side of an inductor and a ground potential. A first power MOSFET supplies an electric current from an input voltage to the input side of the inductor. A second power MOSFET turned on when the first power MOSFET is off allows the input side of the inductor to be of a predetermined potential. A first feedback signal corresponding to an output voltage obtained from the output side of the inductor and a second feedback signal corresponding to an electric current flowed to the first power MOSFET are used to form a PWM signal. The first power MOSFET has plural cells of a vertical type MOS-construction.

    摘要翻译： 开关电源装置对半导体集成电路装置进行快速响应的稳定运行。 在电感器的输出侧和地电位之间提供电容器。 第一功率MOSFET将电流从输入电压提供给电感器的输入侧。 当第一功率MOSFET关断时，第二个功率MOSFET导通，允许电感器的输入侧处于预定电位。 使用对应于从电感器的输出侧获得的输出电压的第一反馈信号和对应于流向第一功率MOSFET的电流的第二反馈信号来形成PWM信号。 第一功率MOSFET具有垂直型MOS结构的多个单元。

    Semiconductor memory having electrically erasable and programmable semiconductor memory cells
    5.
    发明授权
    Semiconductor memory having electrically erasable and programmable semiconductor memory cells 有权
    具有电可擦除和可编程的半导体存储器单元的半导体存储器

    公开(公告)号：US07881111B2

    公开(公告)日：2011-02-01

    申请号：US12504307

    申请日：2009-07-16

    申请人： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    发明人： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

    IPC分类号： G11C16/04

    CPC分类号： G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

    摘要： An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

    摘要翻译： 一种可电气可变的非易失性多级存储器件和操作这种器件的方法，其包括将至少一个存储器单元的状态设置为从包括至少第一至第四电平状态的多个状态中选择的一种状态 响应于要存储在一个存储器单元中的信息，并且通过利用在第二和第二电平状态之间设置的第一参考电平来读取存储单元的状态来确定读出状态是否对应于第一至第四电平状态之一 第三电平状态，在第一和第二电平状态之间设置的第二参考电平和在第三和第四电平状态之间设置的第三参考电平。

    Semiconductor device comprising capacitor and method of fabricating the same
    8.
    发明授权
    Semiconductor device comprising capacitor and method of fabricating the same 有权

    公开(公告)号：US07795648B2

    公开(公告)日：2010-09-14

    申请号：US12368627

    申请日：2009-02-10

    申请人： Yoshinori Tanaka ,  Masahiro Shimizu ,  Hideaki Arima

    发明人： Yoshinori Tanaka ,  Masahiro Shimizu ,  Hideaki Arima

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0629 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

    摘要： A semiconductor device, having a memory cell region and a peripheral circuit region, includes an insulating film, having an upper surface, formed on a major surface of a semiconductor substrate to extend from the memory cell region to the peripheral circuit region. A capacitor lower electrode assembly is formed in the memory cell region to upwardly extend to substantially the same height as the upper surface of the insulating film on the major surface of the semiconductor substrate. Additionally, the lower electrode assembly includes first and second lower electrodes that are adjacent through the insulating film. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. A semiconductor device organized as just described, permits implementation having a high density of integration while ensuring the capacitor exhibits high reliability and a constant capacitance.

    Data processing system and nonvolatile memory
    9.
    发明授权
    Data processing system and nonvolatile memory 有权
    数据处理系统和非易失性存储器

    公开(公告)号：US07773426B2

    公开(公告)日：2010-08-10

    申请号：US12126285

    申请日：2008-05-23

    申请人： Ken Matsubara ,  Yoshinori Takase ,  Tomoyuki Fujisawa

    发明人： Ken Matsubara ,  Yoshinori Takase ,  Tomoyuki Fujisawa

    IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

    CPC分类号： G11C16/3468

    摘要： Erasing is performed with respect to a nonvolatile memory cell without causing depletion halfway therethrough. A control circuit for reversibly and variably controlling the threshold voltage of the nonvolatile memory cell by electrical erasing and writing controls an erase process of performing erasing to the plurality of nonvolatile memory cells assigned to one unit in an erase operation, a first write process of performing writing to the nonvolatile memory cell exceeding a pre-write-back level before a depletion level, and a second write process of performing writing to the nonvolatile memory cell exceeding a write-back level after the first write process. Since the occurrence of depletion is suppressed by successively performing the first write process with respect to the nonvolatile memory cells which may exceed the depletion level in the erase process, erasing can be performed to the nonvolatile memory cell without causing depletion halfway therethrough.

    摘要翻译： 相对于非易失性存储单元执行擦除，而不会通过其中途耗尽。 用于通过电擦除和写入可逆地和可变地控制非易失性存储单元的阈值电压的控制电路控制在擦除操作中分配给一个单元的多个非易失性存储单元执行擦除的擦除处理，执行第一写入处理 在耗尽级别之前写入超过预先写入级别的非易失性存储器单元，以及在第一写入处理之后对超过回写电平的非易失性存储单元执行写入的第二写入处理。 由于通过对于可能超过擦除处理中的耗尽电平的非易失性存储单元连续执行第一写入处理来抑制耗尽的发生，所以可以对非易失性存储单元执行擦除，而不会导致中途耗尽。