公开(公告)号：US20080253215A1

公开(公告)日：2008-10-16

申请号：US11902877

申请日：2007-09-26

申请人： Takesada Akiba ,  Shigeki Ueda ,  Toshikazu Tachibana ,  Masashi Horiguchi

发明人： Takesada Akiba ,  Shigeki Ueda ,  Toshikazu Tachibana ,  Masashi Horiguchi

IPC分类号： G11C5/14 ,  G11C8/00

CPC分类号： G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

摘要： The present invention provides a semiconductor memory circuit capable of reducing current consumption at non-operation in a system equipped with a plurality of chips that share the use of a power supply, address signals and a data bus. The semiconductor memory circuit has an internal circuit which is capable of selectively performing the supply and stop of an operating voltage via switch means and includes a memory array. An input circuit, which receives a predetermined control signal therein, controls the supply and stop of the operating voltage by the switch means to reduce a DC current and a leak current when no memory operation is done, whereby low power consumption can be realized.

摘要翻译： 本发明提供了一种半导体存储器电路，其能够在配备有共享使用电源，地址信号和数据总线的多个芯片的系统中减少非操作时的电流消耗。 半导体存储器电路具有内部电路，其能够选择性地通过开关装置执行工作电压的供应和停止，并且包括存储器阵列。 在其中接收预定控制信号的输入电路通过开关装置控制供电和停止工作电压，以便在不进行存储器操作时减小直流电流和泄漏电流，由此可以实现低功耗。