公开(公告)号：US20120161289A1

公开(公告)日：2012-06-28

申请号：US12977999

申请日：2010-12-23

Applicant: Christiaan J. Werkhoven

Inventor： Christiaan J. Werkhoven

IPC: H01L29/20 ,  H01L21/20

CPC classification number: H01L29/2003 ,  H01L21/02002 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/185 ,  H01L21/242 ,  H01L21/76254 ,  H01L29/0684

Abstract: Methods of fabricating semiconductor structures include forming a plurality of openings extending through a semiconductor material and at least partially through a metal material and deforming the metal material to relax a remaining portion of the semiconductor material. The metal material may be deformed exposing the metal material to a temperature sufficient it to alter (i.e., increase) its ductility. The metal material may be formed from one or more of hafnium, zirconium, yttrium and a metallic glass. Another semiconductor material may be deposited over the remaining portions of the semiconductor material, and a portion the metal material may be removed from between each of the remaining portions of the semiconductor material. Semiconductor structures may be formed using such methods.

Abstract translation: 制造半导体结构的方法包括形成延伸穿过半导体材料并且至少部分地穿过金属材料的多个开口并使金属材料变形以使半导体材料的剩余部分松弛。 金属材料可能变形，使金属材料暴露于足以改变（即增加）其延展性的温度。 金属材料可以由铪，锆，钇和金属玻璃中的一种或多种形成。 可以在半导体材料的剩余部分上沉积另一种半导体材料，并且可以从半导体材料的每个剩余部分之间去除金属材料的一部分。 可以使用这种方法形成半导体结构。

公开(公告)号：US08093077B2

公开(公告)日：2012-01-10

申请号：US12934359

申请日：2009-03-11

Applicant: Hacene Lahreche

Inventor： Hacene Lahreche

IPC: H01L21/00

CPC classification number: H01L21/02458 ,  H01L21/02376 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02598 ,  H01L21/02631

Abstract: The present invention relates to a method for manufacturing a crack free monocrystalline nitride layer having the composition AlxGa1-xN, where 0≦x≦0.3, on a substrate that is likely to generate tensile stress in the layer and to structures containing such layer and substrate. The method includes forming a nucleation layer on the substrate; forming a monocrystalline intermediate layer of aluminum or gallium nitride at a selected thickness on the nucleation layer; forming a monocrystalline seed layer of an AlBN compound in which the boron content is between 0 and 10% at a selected temperature and thickness on the intermediate layer with the thicknesses of the seed and intermediate layers being in a ratio of between 0.05 and 1; and forming the monocrystalline nitride layer of AlxGa1-xN nitride at a selected temperature on the seed layer, with the temperature of formation of the seed layer being 50 to 150° C. higher than the temperature of formation of the monocrystalline nitride layer in order to avoid producing cracks in the monocrystalline nitride layer.

Abstract translation: 本发明涉及一种制造具有组成Al x Ga 1-x N的无裂纹单晶氮化物层的方法，其中0＆lt; NlE; x＆nlE; 0.3在可能在该层中产生拉伸应力的基底上，以及含有该层和基底的结构 。 该方法包括在基板上形成成核层; 在成核层上形成选定厚度的铝或氮化镓的单晶中间层; 在中间层上的选定温度和厚度下形成硼含量为0至10％的AlBN化合物的单晶种子层，其中种子和中间层的厚度为0.05至1的比率; 并且在种子层上在选定温度下形成Al x Ga 1-x N氮化物的单晶氮化物层，晶种层的形成温度比单晶氮化物层的形成温度高50至150℃以便于 避免在单晶氮化物层中产生裂纹。

公开(公告)号：US08062564B2

公开(公告)日：2011-11-22

申请号：US10574120

申请日：2004-09-23

Applicant: Michel Bruel

Inventor： Michel Bruel

IPC: B29C44/34 ,  B29C65/00 ,  H01L21/30 ,  B32B37/00 ,  H01L21/46

CPC classification number: H01L21/76254 ,  C30B29/06 ,  C30B33/02

Abstract: Method for fabricating a structure in the form of a plate, and structure in the form of a plate, in particular formed from silicon, including at least one substrate, a superstrate and at least one intermediate layer interposed between the substrate and the superstrate, in which the intermediate layer comprises at least one base material having distributed therein atoms or molecules termed extrinsic atoms or molecules which differ from the atoms or molecules of the base material, and in which a heat treatment is applied to said plate so that, in the temperature range of said heat treatment, the intermediate layer is plastically deformable and the presence of the selected extrinsic atoms or molecules in the selected base material causes the irreversible formation of micro-bubbles or micro-cavities in the intermediate layer.

Abstract translation: 用于制造板形结构的方法，特别是由硅形成的结构，其中包括至少一个基底，上覆层和插入在基底和底层之间的至少一个中间层 中间层包含至少一种基本材料，其中分布有原子或分子，称为外基原子或分子，其不同于基材的原子或分子，并且其中对所述板施加热处理，使得在温度 所述热处理的范围，所述中间层是塑性变形的，并且所选择的基材中所选择的外在原子或分子的存在导致中间层中的微气泡或微腔的不可逆形成。

公开(公告)号：US20110233720A1

公开(公告)日：2011-09-29

申请号：US13153709

申请日：2011-06-06

Applicant: Eric Neyret ,  Sebastien Kerdiles

Inventor： Eric Neyret ,  Sebastien Kerdiles

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76254

Abstract: A method and/or system are provided for producing a structure comprising a thin layer of semiconductor material on a substrate. The method includes creating an area of embrittlement in the thickness of a donor substrate, bonding the donor substrate with a support substrate and detaching the donor substrate at the level of the area of embrittlement to transfer a thin layer of the donor substrate onto the support substrate. The method also includes thermal treatment of this resulting structure to stabilize the bonding interface between the thin layer and the substrate support. The invention also relates to the structures obtained by such a process.

Abstract translation: 提供了一种方法和/或系统，用于产生包括在衬底上的薄层半导体材料的结构。 该方法包括在施主衬底的厚度上形成脆化区域，用支撑衬底粘合施主衬底，并将施主衬底分离在脆化区域的水平，以将施主衬底的薄层转移到支撑衬底上 。 该方法还包括对所得结构的热处理，以稳定薄层和基底支撑体之间的结合界面。 本发明还涉及通过这种方法获得的结构。

公开(公告)号：US08003493B2

公开(公告)日：2011-08-23

申请号：US12676320

申请日：2008-10-21

Applicant: Nadia Ben Mohamed ,  Sébastien Kerdiles

Inventor： Nadia Ben Mohamed ,  Sébastien Kerdiles

IPC: H01L21/30

CPC classification number: H01L21/187 ,  H01L21/76254

Abstract: A process for splitting a semiconductor substrate having an identification notch on its periphery, by creating a weakened zone in the substrate by implanting atomic species into the substrate while the substrate is held in place on a portion of its periphery during the implanting; and splitting the substrate along the weakened zone by placing the held portion of the substrate in a splitting-wave initiation sector while positioning the notch for initiating a splitting wave followed by the propagation of the wave into the substrate. During splitting the notch is positioned so that it is in a quarter of the periphery of the substrate diametrically opposite the sector for initiating the splitting wave or in the quarter of the periphery of the substrate that is centered on the sector.

Abstract translation: 一种通过在植入期间将衬底保持在其周边的一部分上保持在适当位置的情况下通过将原子物质注入到衬底中而在衬底中产生弱化区域来分裂其外围具有识别缺口的半导体衬底的工艺; 以及通过将衬底的保持部分放置在分裂波起始扇区中并沿着弱化区域分裂衬底，同时定位用于引发分裂波的陷波，随后将波传播到衬底中。 在分割期间，凹口被定位成使得其位于衬底周边的四分之一处，与衬底的圆周方向相反，用于引发分裂波，或者位于以扇形为中心的衬底周边的四分之一部分中。

公开(公告)号：US07981768B2

公开(公告)日：2011-07-19

申请号：US12528573

申请日：2008-04-15

Applicant: Yves-Matthieu Le Vaillant

Inventor： Yves-Matthieu Le Vaillant

IPC: H01L21/30

CPC classification number: H01L21/76251 ,  H01L21/02381 ,  H01L21/0242 ,  H01L21/0245 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02546 ,  H01L21/02664 ,  H01L21/2007

Abstract: A method for producing an epitaxial layer. First, a structure is fabricated by: formation of an intermediate layer on a donor substrate; and formation of the epitaxial layer on the intermediate layer by epitaxy; with the melting temperature of the intermediate layer being lower than the melting temperature of the epitaxial layer; and then a detachment step for transferring the epitaxial layer from the donor substrate. The detachment step includes applying at least one thermal treatment performed at a temperature of between the melting temperature of the intermediate layer and the melting temperature of the epitaxial layer.

Abstract translation: 一种外延层的制造方法。 首先，通过以下步骤制造结构：在施主衬底上形成中间层; 以及通过外延在中间层上形成外延层; 其中间层的熔融温度低于外延层的熔融温度; 然后用于从施主衬底转移外延层的分离步骤。 分离步骤包括在中间层的熔融温度和外延层的熔融温度之间的温度下进行至少一种热处理。

公开(公告)号：US07977747B2

公开(公告)日：2011-07-12

申请号：US12708011

申请日：2010-02-18

Applicant: Frédéric Allibert ,  Sébastien Kerdiles

Inventor： Frédéric Allibert ,  Sébastien Kerdiles

IPC: H01L27/01

CPC classification number: H01L21/76251

Abstract: The invention specifically relates to methods of fabricating a composite substrate by providing a first insulating layer on a support substrate at a thickness of e1 and providing a second insulating layer on a source substrate at a thickness of e2, with each layer having an exposed face for bonding; providing plasma activation energy in an amount sufficient to activate a portion of the thickness of the face of the first insulating layer emp1 and a portion of the thickness of the face of the second insulating layer emp1; providing a final insulating layer by molecular bonding the activated face of the first insulating layer with the activated face of the second insulating layer; and removing a back portion of the source substrate while retaining an active layer comprising a remaining portion of the source substrate bonded to the support substrate with the final insulating layer interposed therein to form the composite substrate. The thicknesses e1, e2 of the first and second insulating layers are sufficient to provide the final insulating layer with a thickness of 50 nanometers or less, and the plasma activation energy and respective thicknesses e1, e2 of the first and second insulating layers are selected such that only respective thicknesses emp1 and emp2 of the faces of the first insulating layer and the second insulating layer are activated.

Abstract translation: 本发明具体涉及通过在e1的厚度上在支撑基板上设置第一绝缘层并以e2的厚度在源极基底上提供第二绝缘层来制造复合衬底的方法，其中每个层具有用于 粘接; 提供足以激活第一绝缘层emp1的表面的厚度的一部分和第二绝缘层emp1的表面的厚度的一部分的量的等离子体激活能; 通过将第一绝缘层的活化面与第二绝缘层的活化面分子结合来提供最终绝缘层; 以及去除源极衬底的后部，同时保持包含源极衬底的剩余部分的活性层，所述剩余部分与所述支撑衬底接合，并且其中插入最终绝缘层以形成所述复合衬底。 第一和第二绝缘层的厚度e1，e2足以提供厚度为50纳米或更小的最终绝缘层，并且选择第一和第二绝缘层的等离子体激活能和各自的厚度e1，e2， 仅激活第一绝缘层和第二绝缘层的面的相应厚度emp1和emp2。

公开(公告)号：US20110163410A1

公开(公告)日：2011-07-07

申请号：US12663096

申请日：2008-06-06

Applicant: Thomas Signamarcheix ,  Franck Fournel ,  Hubert Moriceau

Inventor： Thomas Signamarcheix ,  Franck Fournel ,  Hubert Moriceau

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/8258 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

Abstract: A method for producing a hybrid substrate, including a support substrate, a continuous buried insulator layer and, on this continuous layer, a hybrid layer including alternating zones of a first material and at least one second material, wherein these two materials are different by their nature and/or their crystallographic characteristics. The method forms a hybrid layer, including alternating zones of first and second materials, on a homogeneous substrate, assembles this hybrid layer, the continuous insulator layer and the support substrate, and eliminates a part at least of the homogeneous substrate, before or after the assembling.

Abstract translation: 一种制造混合基板的方法，包括支撑基板，连续埋层绝缘体层，并且在该连续层上，包括第一材料和至少一种第二材料的交替区域的混合层，其中这两种材料由它们 性质和/或其晶体学特征。 该方法形成混合层，包括在均匀基底上的第一和第二材料的交替区，组装该混合层，连续绝缘体层和支撑衬底，并且在第一和第二材料之前或之后形成至少均匀的衬底的部分 组装。

公开(公告)号：US07892951B2

公开(公告)日：2011-02-22

申请号：US12237000

申请日：2008-09-24

Applicant: Didier Landru ,  Sébastien Kerdiles

Inventor： Didier Landru ,  Sébastien Kerdiles

IPC: H01L21/20 ,  H01L21/46 ,  H01L21/568 ,  H01L21/569 ,  H01L21/57

CPC classification number: H01L21/2007 ,  H01L21/76254

Abstract: A method of producing a semiconductor structure having a buried insulating layer having a thickness between 2 and 25 nm, by: forming at least one insulating layer on a surface of a first or second substrate, or both, wherein the surfaces are free from an insulator or presenting a native oxide layer resulting from exposure of the substrates to ambient conditions; assembling the first and second substrates; and thinning down the first substrate, in order to obtain the semiconductor structure. In this method, the insulating layer forming stage is a plasma activation based on an oxidizing or nitriding gas.

Abstract translation: 一种制造半导体结构的方法，该半导体结构具有通过在第一或第二基板或两者的表面上形成至少一个绝缘层而具有2至25nm厚度的掩埋绝缘层，其中所述表面不含绝缘体 或呈现由底物暴露于环境条件而产生的天然氧化物层; 组装第一和第二基板; 并使第一衬底变薄，以获得半导体结构。 在该方法中，绝缘层形成阶段是基于氧化或氮化气体的等离子体激活。

公开(公告)号：US07807548B2

公开(公告)日：2010-10-05

申请号：US11827715

申请日：2007-07-13

Applicant: Bernard Aspar ,  Chrystelle Lagahe Blanchard ,  Nicolas Sousbie

Inventor： Bernard Aspar ,  Chrystelle Lagahe Blanchard ,  Nicolas Sousbie

IPC: H01L21/30

CPC classification number: B81B3/001 ,  B81C1/00952 ,  B81C2201/115

Abstract: The invention provides a method for forming a semiconductor component with a rough buried interface. The method includes providing a first semiconductor substrate having a first surface of roughness R1. The method further includes thermally oxidizing the first surface of the first semiconductor substrate to form an oxide layer defining an external oxide surface on the first semiconductor substrate and a buried oxide-semiconductor interface below the oxide surface, so that the buried oxide surface has a roughness R2 that is less than R1. The method also includes assembling the oxide surface of the first semiconductor substrate with a second substrate. The invention also provides a component formed according to the method of the invention.

Abstract translation: 本发明提供一种用于形成具有粗糙掩埋界面的半导体部件的方法。 该方法包括提供具有粗糙度R1的第一表面的第一半导体衬底。 该方法还包括热氧化第一半导体衬底的第一表面以形成限定第一半导体衬底上的外部氧化物表面的氧化物层和氧化物表面下方的掩埋氧化物半导体界面，使得掩埋氧化物表面具有粗糙度 R2小于R1。 该方法还包括用第二衬底组装第一半导体衬底的氧化物表面。 本发明还提供了根据本发明的方法形成的部件。