公开(公告)号：US20160351486A1

公开(公告)日：2016-12-01

申请号：US14722872

申请日：2015-05-27

Applicant: STATS ChipPAC, Ltd.

Inventor： JinHee Jung ,  HyungSang Park ,  SungSoo Kim

IPC: H01L23/498 ,  H01L49/02 ,  H01L21/48

CPC classification number: H01L28/40 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49827 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/25 ,  H01L2221/68345 ,  H01L2224/04105 ,  H01L2224/2518 ,  H01L2224/32225 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83005 ,  H01L2224/92144 ,  H05K1/185 ,  H05K3/4664 ,  H05K2201/10015

Abstract: A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.

Abstract translation: 半导体器件包括第一导电层。 在第一导电层上形成第二导电层。 半导体部件设置在第一导电层上。 第二导电层位于半导体部件的顶表面和半导体部件的底表面之间的平面中。 在与第一导电层相对的半导体部件上形成第三导电层。 半导体器件包括对称结构。 在第一导电层和半导体部件之间形成第一绝缘层。 在半导体部件和第三导电层之间形成第二绝缘层。 第一导电层和半导体部件之间的第一绝缘层的高度在半导体部件和第三导电层之间的第二绝缘层的高度的90％至110％之间。 半导体部件包括无源器件。

公开(公告)号：US20160276307A1

公开(公告)日：2016-09-22

申请号：US14660840

申请日：2015-03-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L25/16 ,  H01L23/552 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L25/00 ,  H01L21/66

CPC classification number: H01L24/17 ,  H01L21/561 ,  H01L21/568 ,  H01L22/14 ,  H01L23/13 ,  H01L23/3135 ,  H01L23/36 ,  H01L23/3737 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5389 ,  H01L23/552 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/17515 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/81 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2225/1035 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/143 ,  H01L2924/1433 ,  H01L2924/14335 ,  H01L2924/1461 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3511 ,  H01L2224/03 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

Abstract: A PoP semiconductor device has a top semiconductor package disposed over a bottom semiconductor package. The top semiconductor package has a substrate and a first semiconductor die disposed over the substrate. First and second encapsulants are deposited over the first semiconductor die and substrate. A first build-up interconnect structure is formed over the substrate after depositing the second encapsulant. The top package is disposed over the bottom package. The bottom package has a second semiconductor die and modular interconnect units disposed around the second semiconductor die. A second build-up interconnect structure is formed over the second semiconductor die and modular interconnect unit. The modular interconnect units include a plurality of conductive vias and a plurality of contact pads electrically connected to the conductive vias. The I/O pattern of the build-up interconnect structure on the top semiconductor package is designed to coincide with the I/O pattern of the modular interconnect units.

Abstract translation: PoP半导体器件具有设置在底部半导体封装上的顶部半导体封装。 顶部半导体封装具有衬底和设置在衬底上的第一半导体管芯。 第一和第二密封剂沉积在第一半导体管芯和衬底上。 在沉积第二密封剂之后，在衬底上形成第一叠层互连结构。 顶部包装被放置在底部包装上。 底部封装具有设置在第二半导体管芯周围的第二半导体管芯和模块化互连单元。 在第二半导体管芯和模块化互连单元上形成第二堆叠互连结构。 模块化互连单元包括多个导电通孔和电连接到导电通孔的多个接触垫。 顶部半导体封装上的积聚互连结构的I / O图案被设计成与模块化互连单元的I / O模式一致。

公开(公告)号：US20160214857A1

公开(公告)日：2016-07-28

申请号：US15008347

申请日：2016-01-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Yaojian Lin ,  Il Kwon Shim

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81B7/007 ,  B81B2201/0257 ,  B81B2207/012 ,  B81B2207/096 ,  H01L2224/48091 ,  H01L2924/15151 ,  H01L2924/00014

Abstract: A microelectromechanical system (MEMS) semiconductor device has a first and second semiconductor die. A first semiconductor die is embedded within an encapsulant together with a modular interconnect unit. Alternatively, the first semiconductor die is embedded within a substrate. A second semiconductor die, such as a MEMS die, is disposed over the first semiconductor die and electrically connected to the first semiconductor die through an interconnect structure. In another embodiment, the first semiconductor die is flip chip mounted to the substrate, and the second semiconductor die is wire bonded to the substrate adjacent to the first semiconductor die. In another embodiment, first and second semiconductor die are embedded in an encapsulant and are electrically connected through a build-up interconnect structure. A lid is disposed over the semiconductor die. In a MEMS microphone embodiment, the lid, substrate, or interconnect structure includes an opening over a surface of the MEMS die.

Abstract translation: 微机电系统（MEMS）半导体器件具有第一和第二半导体管芯。 第一半导体管芯与模块化互连单元一起嵌入密封剂内。 或者，第一半导体管芯被嵌入到衬底内。 第二半导体管芯，例如MEMS管芯，设置在第一半导体管芯上，并通过互连结构电连接到第一半导体管芯。 在另一个实施例中，第一半导体管芯是倒装芯片安装到衬底，并且第二半导体管芯与第一半导体管芯相邻的衬底引线接合。 在另一个实施例中，第一和第二半导体管芯被嵌入密封剂中并通过堆积互连结构电连接。 盖子设置在半导体管芯上。 在MEMS麦克风实施例中，盖，基板或互连结构包括在MEMS管芯的表面上的开口。

公开(公告)号：US09349723B2

公开(公告)日：2016-05-24

申请号：US13365097

申请日：2012-02-02

Applicant: Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Robert C. Frye

Inventor： Yaojian Lin ,  Haijing Cao ,  Qing Zhang ,  Robert C. Frye

IPC: H01L27/07 ,  H01G4/228 ,  H01G4/33 ,  H01L27/01 ,  H01L23/522 ,  H01L23/00 ,  H01L49/02

CPC classification number: H01L27/0794 ,  H01G4/228 ,  H01G4/33 ,  H01L23/5223 ,  H01L23/5227 ,  H01L23/5228 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L27/016 ,  H01L28/40 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0346 ,  H01L2224/0391 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05181 ,  H01L2224/05186 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/11334 ,  H01L2224/1146 ,  H01L2224/1148 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/73207 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/01074 ,  H01L2924/04953 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A flip chip semiconductor device has a substrate with a plurality of active devices formed thereon. A passive device is formed on the substrate by depositing a first conductive layer over the substrate, depositing an insulating layer over the first conductive layer, and depositing a second conductive layer over the insulating layer. The passive device is a metal-insulator-metal capacitor. The deposition of the insulating layer and first and second conductive layers is performed without photolithography. An under bump metallization (UBM) layer is formed on the substrate in electrical contact with the plurality of active devices. A solder bump is formed over the UBM layer. The passive device can also be a resistor by depositing a resistive layer over the first conductive layer and depositing a third conductive layer over the resistive layer. The passive device electrically contacts the solder bump.

Abstract translation: 倒装芯片半导体器件具有在其上形成有多个有源器件的衬底。 通过在衬底上沉积第一导电层，在第一导电层上沉积绝缘层，以及在绝缘层上沉积第二导电层，在衬底上形成无源器件。 无源器件是金属 - 绝缘体 - 金属电容器。 绝缘层和第一和第二导电层的沉积在没有光刻的情况下进行。 在与多个有源器件电接触的衬底上形成凸块下金属化（UBM）层。 在UBM层上形成焊料凸块。 无源器件还可以是通过在第一导电层上沉积电阻层并在电阻层上沉积第三导电层的电阻器。 无源器件与焊料凸块电接触。

公开(公告)号：US20160141238A1

公开(公告)日：2016-05-19

申请号：US15007518

申请日：2016-01-27

Applicant: STATS ChipPAC, Ltd.

Inventor： Seung Wook Yoon ,  Jose A. Caparas ,  Yaojian Lin ,  Pandi C. Marimuthu ,  Kang Chen ,  Xusheng Bao ,  Jianmin Fang

IPC: H01L23/498 ,  H01L21/768 ,  H01L21/311 ,  H01L25/10

CPC classification number: H01L23/49827 ,  H01L21/311 ,  H01L21/56 ,  H01L21/561 ,  H01L21/568 ,  H01L21/76804 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/19 ,  H01L24/96 ,  H01L24/97 ,  H01L25/105 ,  H01L2224/12105 ,  H01L2224/97 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/3511 ,  H01L2924/00 ,  H01L2224/19 ,  H01L2924/00012

Abstract: A semiconductor device has a semiconductor die with an encapsulant deposited over and around the semiconductor die. An interconnect structure is formed over a first surface of the encapsulant. An opening is formed from a second surface of the encapsulant to the first surface of the encapsulant to expose a surface of the interconnect structure. A bump is formed recessed within the opening and disposed over the surface of the interconnect structure. A semiconductor package is provided. The semiconductor package is disposed over the second surface of the encapsulant and electrically connected to the bump. A plurality of interconnect structures is formed over the semiconductor package to electrically connect the semiconductor package to the bump. The semiconductor package includes a memory device. The semiconductor device includes a height less than 1 millimeter. The opening includes a tapered sidewall formed by laser direct ablation.

Abstract translation: 半导体器件具有沉积在半导体管芯上方和周围的具有密封剂的半导体管芯。 在密封剂的第一表面上形成互连结构。 开口由密封剂的第二表面形成到密封剂的第一表面以暴露互连结构的表面。 凸起凹陷形成在开口内并设置在互连结构的表面上。 提供半导体封装。 半导体封装设置在密封剂的第二表面上并电连接到凸块。 多个互连结构形成在半导体封装上，以将半导体封装电连接到凸块。 半导体封装包括存储器件。 半导体器件包括高度小于1毫米的半导体器件。 开口包括通过激光直接消融形成的锥形侧壁。

公开(公告)号：US09343396B2

公开(公告)日：2016-05-17

申请号：US13543088

申请日：2012-07-06

Applicant: Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

Inventor： Yaojian Lin ,  Robert C. Frye ,  Pandi Chelvam Marimuthu ,  Kai Liu

IPC: H01L25/16 ,  H01L23/552 ,  H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L21/4857 ,  H01L21/561 ,  H01L21/568 ,  H01L23/49822 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/0346 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05671 ,  H01L2224/1132 ,  H01L2224/11334 ,  H01L2224/1145 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/13111 ,  H01L2224/14133 ,  H01L2224/14135 ,  H01L2224/14163 ,  H01L2224/14165 ,  H01L2224/2101 ,  H01L2224/214 ,  H01L2224/221 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/30105 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012

Abstract: A semiconductor wafer contains semiconductor die. A first conductive layer is formed over the die. A resistive layer is formed over the die and first conductive layer. A first insulating layer is formed over the die and resistive layer. The wafer is singulated to separate the die. The die is mounted to a temporary carrier. An encapsulant is deposited over the die and carrier. The carrier and a portion of the encapsulant and first insulating layer is removed. A second insulating layer is formed over the encapsulant and first insulating layer. A second conductive layer is formed over the first and second insulating layers. A third insulating layer is formed over the second insulating layer and second conductive layer. A third conductive layer is formed over the third insulating layer and second conductive layer. A fourth insulating layer is formed over the third insulating layer and third conductive layer.

Abstract translation: 半导体晶片包含半导体晶片。 在模具上形成第一导电层。 在管芯和第一导电层上形成电阻层。 在管芯和电阻层上形成第一绝缘层。 将晶片单片化以分离模具。 模具安装到临时托架上。 密封剂沉积在模具和载体上。 移除载体和密封剂和第一绝缘层的一部分。 在密封剂和第一绝缘层之上形成第二绝缘层。 在第一绝缘层和第二绝缘层上形成第二导电层。 在第二绝缘层和第二导电层上形成第三绝缘层。 在第三绝缘层和第二导电层上形成第三导电层。 在第三绝缘层和第三导电层上形成第四绝缘层。

公开(公告)号：US09331002B2

公开(公告)日：2016-05-03

申请号：US13944783

申请日：2013-07-17

Applicant: STATS ChipPAC, Ltd.

Inventor： Reza A. Pagaila ,  Byung Tai Do ,  Linda Pei Ee Chua

IPC: H01L21/30 ,  H01L23/48 ,  H01L21/683 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/50

CPC classification number: H01L23/481 ,  H01L21/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3157 ,  H01L24/18 ,  H01L24/19 ,  H01L24/48 ,  H01L24/73 ,  H01L24/82 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2224/02371 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/18 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82039 ,  H01L2224/9222 ,  H01L2224/92244 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19107 ,  H01L2924/30105 ,  H01L2224/82 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device is made by providing a first semiconductor wafer having semiconductor die. A gap is made between the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a first through hole via (THV). A conductive lining is conformally deposited in the first THV. A solder material is disposed above the conductive lining of the first THV. A second semiconductor wafer having semiconductor die is disposed over the first wafer. A second THV is formed in a gap between the die of the second wafer. A conductive lining is conformally deposited in the second THV. A solder material is disposed above the second THV. The second THV is aligned to the first THV. The solder material is reflowed to form the conductive vias within the gap. The gap is singulated to separate the semiconductor die.

公开(公告)号：US09324659B2

公开(公告)日：2016-04-26

申请号：US13195636

申请日：2011-08-01

Applicant: SungWon Cho ,  DaeSik Choi ,  HyungSang Park ,  DongSoo Moon

Inventor： SungWon Cho ,  DaeSik Choi ,  HyungSang Park ,  DongSoo Moon

IPC: H01L21/00 ,  H01L23/538 ,  H01L23/498 ,  H01L21/56 ,  H01L23/00 ,  H01L21/683 ,  H01L25/03 ,  H01L25/065 ,  H01L25/00 ,  H01L23/31

CPC classification number: H01L23/5389 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/73 ,  H01L24/96 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/05553 ,  H01L2224/12105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2225/06548 ,  H01L2225/06558 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A semiconductor device has a first semiconductor wafer mounted to a carrier. A second semiconductor wafer is mounted to the first semiconductor wafer. The first and second semiconductor wafers are singulated to separate stacked first and second semiconductor die. A peripheral region between the stacked semiconductor die is expanded. A conductive layer is formed over the carrier between the stacked semiconductor die. Alternatively, a conductive via is formed partially through the carrier. A bond wire is formed between contact pads on the second semiconductor die and the conductive layer or conductive via. An encapsulant is deposited over the stacked semiconductor die, bond wire, and carrier. The carrier is removed to expose the conductive layer or conductive via and contact pads on the first semiconductor die. Bumps are formed directly on the conductive layer and contact pads on the first semiconductor die.

Abstract translation: 半导体器件具有安装到载体上的第一半导体晶片。 第二半导体晶片安装到第一半导体晶片。 单个第一和第二半导体晶片以分离堆叠的第一和第二半导体管芯。 层叠的半导体管芯之间的周边区域扩大。 在层叠的半导体管芯之间的载体上形成导电层。 或者，导电通孔部分地通过载体形成。 在第二半导体管芯上的接触焊盘和导电层或导电通孔之间形成接合线。 密封剂沉积在堆叠的半导体管芯，接合线和载体上。 去除载体以暴露第一半导体管芯上的导电层或导电通孔和接触焊盘。 直接在导电层和第一半导体管芯上的接触焊盘上形成凸起。

公开(公告)号：US09318380B2

公开(公告)日：2016-04-19

申请号：US14330704

申请日：2014-07-14

Applicant: STATS ChipPAC, Ltd.

Inventor： YoungJoon Kim ,  SangMi Park ,  YongHyuk Jeong

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L21/683 ,  H01L23/498 ,  H01L23/31 ,  H01L25/03 ,  H01L25/10

CPC classification number: H01L21/76877 ,  H01L21/561 ,  H01L21/565 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/80 ,  H01L24/96 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68363 ,  H01L2221/68381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/16225 ,  H01L2224/19 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2924/01029 ,  H01L2924/01322 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/19107 ,  H01L2224/81 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/11 ,  H01L2224/03

Abstract: A semiconductor device has a first conductive layer formed over a first substrate. A second conductive layer is formed over a second substrate. A first semiconductor die is mounted to the first substrate and electrically connected to the first conductive layer. A second semiconductor die is mounted to the second substrate and electrically connected to the second conductive layer. The first semiconductor die is mounted over the second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and the first and second substrates. A conductive interconnect structure is formed through the encapsulant to electrically connect the first and second semiconductor die to the second surface of the semiconductor device. Forming the conductive interconnect structure includes forming a plurality of conductive vias through the encapsulant and the first substrate outside a footprint of the first and second semiconductor die.

Abstract translation: 半导体器件具有形成在第一衬底上的第一导电层。 在第二衬底上形成第二导电层。 第一半导体管芯安装到第一基板并电连接到第一导电层。 第二半导体管芯安装到第二衬底并电连接到第二导电层。 第一半导体管芯安装在第二半导体管芯上。 密封剂沉积在第一和第二半导体管芯以及第一和第二衬底上。 通过密封剂形成导电互连结构，以将第一和第二半导体管芯电连接到半导体器件的第二表面。 形成导电互连结构包括在第一和第二半导体管芯的覆盖区之外形成通过密封剂和第一衬底的多个导电通孔。

公开(公告)号：US20160104731A1

公开(公告)日：2016-04-14

申请号：US14974002

申请日：2015-12-18

Applicant: STATS ChipPAC, Ltd.

Inventor： Seng Guan Chow ,  Lee Sun Lim ,  Rui Huang ,  Xu Sheng Bao ,  Ma Phoo Pwint Hlaing

IPC: H01L27/146 ,  H01L21/768 ,  B81C1/00 ,  H01L31/0203 ,  H01L25/16

CPC classification number: H01L27/1469 ,  B81C1/0023 ,  H01L21/76898 ,  H01L25/165 ,  H01L25/167 ,  H01L27/14618 ,  H01L27/14634 ,  H01L27/14636 ,  H01L31/0203 ,  H01L2224/73265 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/1461 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device has a substrate containing a transparent or translucent material. A spacer is mounted to the substrate. A first semiconductor die has an active region and first conductive vias electrically connected to the active region. The active region can include a sensor responsive to light received through the substrate. The first die is mounted to the spacer with the active region positioned over an opening in the spacer and oriented toward the substrate. An encapsulant is deposited over the first die and substrate. An interconnect structure is formed over the encapsulant and first die. The interconnect structure is electrically connected through the first conductive vias to the active region. A second semiconductor die having second conductive vias can be mounted to the first die with the first conductive vias electrically connected to the second conductive vias.

Abstract translation: 半导体器件具有含有透明或半透明材料的衬底。 衬垫安装到衬底上。 第一半导体管芯具有有源区和电连接到有源区的第一导电通孔。 有源区域可以包括响应于通过衬底接收的光的传感器。 第一管芯安装到间隔件上，其中有源区域位于间隔件中的开口上方并朝向衬底。 密封剂沉积在第一裸片和衬底上。 在密封剂和第一模具上形成互连结构。 互连结构通过第一导电通孔电连接到有源区。 具有第二导电通孔的第二半导体管芯可以被安装到第一管芯，其中第一导电通孔电连接到第二导电通孔。