公开(公告)号：US12255152B2

公开(公告)日：2025-03-18

申请号：US18359688

申请日：2023-07-26

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： ChangOh Kim ,  JinHee Jung ,  JiWon Lee ,  YuJeong Jang

IPC: H01L23/552 ,  H01L21/3213 ,  H01L23/31 ,  H01L25/065

Abstract: A semiconductor device is formed by providing a semiconductor package including a shielding layer and forming a slot in the shielding layer using a laser. The laser is turned on and exposed to the shielding layer with a center of the laser disposed over a first point of the shielding layer. The laser is moved in a loop while the laser remains on and exposed to the shielding layer. Exposure of the laser to the shielding layer is stopped when the center of the laser is disposed over a second point of the shielding layer. A distance between the first point and the second point is approximately equal to a radius of the laser.

公开(公告)号：US20250079380A1

公开(公告)日：2025-03-06

申请号：US18459777

申请日：2023-09-01

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  SeungHyun Lee

IPC: H01L23/00

Abstract: A semiconductor device has a carrier. An electrical component is disposed over the carrier. An encapsulant is deposited over the electrical component. A conductive layer is formed over the encapsulant. The conductive layer is deposited as a plurality of graphene-coated metal balls in a matrix. The conductive layer is sintered by intensive pulsed light (IPL) irradiation.

公开(公告)号：US20250079372A1

公开(公告)日：2025-03-06

申请号：US18459196

申请日：2023-08-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： KyuWon Lee ,  JiWon Jang ,  Myeongjin Kim ,  HyeSun Kim ,  YoungDeuk Lee ,  YoungJin Woo

IPC: H01L23/00

Abstract: A semiconductor device has a semiconductor wafer or substrate including a plurality of semiconductor die. A plurality of first bumps is formed over an active surface of the semiconductor wafer. A plurality of second bumps is formed within a saw street of the semiconductor wafer separating the plurality of semiconductor die. A top surface of the first bumps is coplanar with a top surface of the second bumps. The second bumps are formed within a first saw street of the semiconductor wafer and further within a second saw street of the semiconductor wafer different from the first saw street. The first bumps are electrically connected to the semiconductor die to provide a function for the semiconductor die. The second bumps are dummy bumps that have no electrical function for the semiconductor die. The semiconductor wafer is singulated through the saw street and second bumps.

公开(公告)号：US20240421024A1

公开(公告)日：2024-12-19

申请号：US18816920

申请日：2024-08-27

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： KyungOe Kim ,  Wagno Alves Braganca, JR. ,  DongSam Park

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

Abstract: A semiconductor device has a heat spreader with an opening formed through the heat spreader. The heat spreader is disposed over a substrate with a semiconductor die disposed on the substrate in the opening. A thermally conductive material, e.g., adhesive or an elastomer plug, is disposed in the opening between the heat spreader and semiconductor die. A conductive layer is formed over the substrate, heat spreader, and thermally conductive material.

公开(公告)号：US20240371825A1

公开(公告)日：2024-11-07

申请号：US18646853

申请日：2024-04-26

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： TaeWoo LEE ,  HeeSoo LEE ,  EunHee MYUNG

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L25/00

Abstract: A semiconductor package and a method for making the same are provided. The semiconductor package may include: a substrate having a first surface and a second surface opposite to the first surface; a first insulating layer disposed on the first surface of the substrate and having a first concave portion; a first semiconductor interposer disposed in the first concave portion of the first insulating layer, the first semiconductor interposer including a first semiconductor layer and a plurality of first wiring patterns formed on the first semiconductor layer; a first electronic component overlapping with a first portion of the first semiconductor interposer and electrically connected with the first wiring patterns of the first semiconductor interposer; and a second electronic component overlapping with a second portion of the first semiconductor interposer and electrically connected with the first wiring patterns of the first semiconductor interposer.

公开(公告)号：US20240332035A1

公开(公告)日：2024-10-03

申请号：US18193942

申请日：2023-03-31

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  SuJeong Kwon

IPC: H01L21/56 ,  H01L23/29 ,  H01L23/31 ,  H01L23/538 ,  H01L25/065

CPC classification number: H01L21/565 ,  H01L21/563 ,  H01L23/295 ,  H01L23/3128 ,  H01L23/5389 ,  H01L25/0657 ,  H01L2225/06548

Abstract: A semiconductor device has a substrate and a first electrical component disposed over the substrate. A first encapsulant is deposited over the first electrical component and substrate. An interconnect structure including a graphene core shell is formed over or through the first encapsulant. The graphene core shell has a copper core or silver core. The interconnect structure has a plurality of cores covered by graphene and the graphene is interconnected within the interconnect structure to form an electrical path. The interconnect structure has thermoset material or polymer or composite epoxy type matrix and the graphene core shell is embedded within the thermoset material or polymer or composite epoxy type matrix. A second electrical component is disposed over the first encapsulant. A second encapsulant is deposited over the second electrical component. A shielding layer is formed over the second encapsulant. The shielding layer can have a graphene core shell.

公开(公告)号：US20240312884A1

公开(公告)日：2024-09-19

申请号：US18184649

申请日：2023-03-15

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： YongMoo Shin ,  HeeSoo Lee ,  SeungHyun Lee

IPC: H01L23/498 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49811 ,  H01L21/563 ,  H01L23/3128 ,  H01L25/18

Abstract: A semiconductor device has a substrate and an electrical component disposed over a first surface of the substrate. A first encapsulant is deposited over the first surface of the substrate. A second encapsulant is deposited over a second surface of the substrate with a via formed in the second encapsulant. A conductive material containing a graphene core shell is deposited in the via in the second encapsulant to form a conductive post. The graphene core shell can have a copper core with a graphene coating formed over the copper core. The conductive material has a matrix to embed the graphene core shell. The conductive material can have a plurality of cores covered by graphene and the graphene is interconnected within the conductive material to form an electrical path. The conductive material can have thermoset material or polymer or composite epoxy type matrix to embed the graphene core shell.

公开(公告)号：US12094843B2

公开(公告)日：2024-09-17

申请号：US17817481

申请日：2022-08-04

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Pandi Chelvam Marimuthu ,  Andy Chang Bum Yong ,  Aung Kyaw Oo ,  Yaojian Lin

IPC: H01L23/66 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/538 ,  H01L23/552

CPC classification number: H01L23/66 ,  H01L21/486 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5225 ,  H01L23/528 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L24/96 ,  H01L24/97 ,  H01L23/3128 ,  H01L23/49833 ,  H01L2221/68331 ,  H01L2221/68345 ,  H01L2221/68354 ,  H01L2221/68359 ,  H01L2223/6677 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/19 ,  H01L2224/24227 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83 ,  H01L2224/83005 ,  H01L2224/92244 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/3511

Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A first conductive layer is formed with an antenna over a first surface of the encapsulant. A second conductive layer is formed with a ground plane over a second surface of the encapsulant with the antenna located within a footprint of the ground plane. A conductive bump is formed on the ground plane. A third conductive layer is formed over the first surface of the encapsulant. A fourth conductive layer is formed over the second surface of the encapsulant. A conductive via is disposed adjacent to the semiconductor die prior to depositing the encapsulant. The antenna is coupled to the semiconductor die through the conductive via. The antenna is formed with the conductive via between the antenna and semiconductor die. A PCB unit is disposed in the encapsulant.

公开(公告)号：US12094729B2

公开(公告)日：2024-09-17

申请号：US17457719

申请日：2021-12-06

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Yaojian Lin ,  Heinz-Peter Wirtz ,  Seung Wook Yoon ,  Pandi C. Marimuthu

IPC: H01L23/28 ,  H01L21/3105 ,  H01L21/56 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L21/565 ,  H01L21/31058 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L21/78 ,  H01L23/28 ,  H01L23/3114 ,  H01L23/3121 ,  H01L23/3128 ,  H01L23/3135 ,  H01L23/3142 ,  H01L24/11 ,  H01L24/81 ,  H01L24/96 ,  H01L24/97 ,  H01L21/568 ,  H01L2224/0508 ,  H01L2224/05111 ,  H01L2224/05124 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05171 ,  H01L2224/05172 ,  H01L2224/05184 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/13113 ,  H01L2224/13116 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/01322 ,  H01L2924/10252 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/97 ,  H01L2224/73265 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2924/00 ,  H01L2924/12041 ,  H01L2924/00 ,  H01L2924/1306 ,  H01L2924/00 ,  H01L2924/01322 ,  H01L2924/00 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/12042 ,  H01L2924/00 ,  H01L2224/1134 ,  H01L2924/00014 ,  H01L2924/00011 ,  H01L2224/81805

Abstract: A semiconductor device has a semiconductor wafer including a plurality of semiconductor die. An insulating layer is formed over the semiconductor wafer. A portion of the insulating layer is removed by LDA to expose a portion of an active surface of the semiconductor die. A first conductive layer is formed over a contact pad on the active surface of the semiconductor die. The semiconductor wafer is singulated to separate the semiconductor die. The semiconductor die is disposed over a carrier with the active surface of the semiconductor die offset from the carrier. An encapsulant is deposited over the semiconductor die and carrier to cover a side of the semiconductor die and the exposed portion of the active surface. An interconnect structure is formed over the first conductive layer. Alternatively, a MUF material is deposited over a side of the semiconductor die and the exposed portion of the active surface.

公开(公告)号：US20240213231A1

公开(公告)日：2024-06-27

申请号：US18599304

申请日：2024-03-08

Applicant: STATS ChipPAC Pte. Ltd.

Inventor： Junghwan Jang ,  Giwoong Nam ,  Myongsuk Kang

IPC: H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L21/4853 ,  H01L21/4857 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/20 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/214 ,  H01L2225/1035 ,  H01L2225/1058

Abstract: A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.