公开(公告)号：US09019140B2

公开(公告)日：2015-04-28

申请号：US14028244

申请日：2013-09-16

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Jian Hua Zhao ,  Yuxing Zhang

IPC: H03M1/38 ,  H03M1/06 ,  H03M1/46

CPC classification number: H03M1/06 ,  H03M1/0604 ,  H03M1/0695 ,  H03M1/468

Abstract: In one embodiment, a method for converting an analog input value to a digital output value is disclosed. A successive approximation is performed. The analog input is quantized to a first quantized value, which is converted to a first analog value using a DAC. The first analog value is subtracted from the analog input value to form a first residue. The first residue is quantized to form a second quantized value, and a second residue is formed by converting the second quantized value to a second analog value using the DAC and subtracting the second analog value from the first residue value. The second residue is then quantized to form a third quantized value. The first, second and third quantized values are converted into a digital output value. The first, second and third quantized values each have at least three levels.

Abstract translation: 在一个实施例中，公开了一种将模拟输入值转换为数字输出值的方法。 执行逐次逼近。 模拟输入被量化为第一量化值，其使用DAC被转换为第一模拟值。 从模拟输入值中减去第一个模拟值，形成第一个残差。 量化第一残余物以形成第二量化值，并且通过使用DAC将第二量化值转换为第二模拟值并从第一残留值减去第二模拟值来形成第二残差。 然后将第二残基量化以形成第三量子化值。 第一，第二和第三量化值被转换为数字输出值。 第一，第二和第三量化值各自至少有三个等级。

公开(公告)号：US08928360B2

公开(公告)日：2015-01-06

申请号：US13854395

申请日：2013-04-01

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Jian Hua Zhao ,  Wadeo Ou

IPC: H03K3/00 ,  H03G3/00 ,  H03G3/30

CPC classification number: H03G3/004 ,  H03G3/002 ,  H03G3/3089

Abstract: Circuits and methods to realize a power-efficient high frequency buffer. The amplitude of a buffered signal is detected and compared with the amplitude of the input signal. The comparison result can be fed back to the digitally-controlled buffer to keep the output gain constant. By using feedback control, the buffer can be kept at the most suitable biasing condition even if the load condition or signal frequency varies.

Abstract translation: 实现功率高效的高频缓冲器的电路和方法。 检测缓冲信号的幅度并与输入信号的幅度进行比较。 比较结果可以反馈到数字控制缓冲器，以保持输出增益不变。 通过使用反馈控制，即使负载条件或信号频率变化，也可以将缓冲器保持在最合适的偏置状态。

公开(公告)号：US08729927B2

公开(公告)日：2014-05-20

申请号：US13657930

申请日：2012-10-23

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Ming Jiang ,  Jerry Cui

IPC: H03K3/00

CPC classification number: H03K17/102

Abstract: A drive circuit includes a switching transistor having a design maximum voltage V2 and a cascode transistor having a design maximum voltage V1, wherein the cascode transistor is source-drain coupled in series with the switching transistor. The circuit further includes a current source coupled between an intermediate voltage node and a gate of the cascode transistor. If the drive circuit is a low side driver, the intermediate voltage node receives an intermediate voltage Vmed set below a high supply voltage Vhigh and that meets the following conditions: a) Vmed

Abstract translation: 驱动电路包括具有设计最大电压V2的开关晶体管和具有设计最大电压V1的共源共栅晶体管，其中共源共栅晶体管是与开关晶体管串联耦合的源极 - 漏极。 电路还包括耦合在中间电压节点和共源共栅晶体管的栅极之间的电流源。 如果驱动电路是低端驱动器，则中间电压节点接收设置在高电源电压Vhigh以下的中间电压Vmed，并满足以下条件：a）Vmed <= V2和b）Vhigh-Vmed <= V1。 如果驱动电路是高侧驱动器，则中间电压节点接收低于高电源电压的中间电压Vmed，并且符合以下条件：a）Vmed <= V1和b）Vhigh-Vmed <= V2。 该电路可以通过将高侧驱动器和低侧驱动器串联耦合而构造为推挽驱动器。

公开(公告)号：US08237596B2

公开(公告)日：2012-08-07

申请号：US12964228

申请日：2010-12-09

Applicant: Jianhua Zhao ,  Yuan Yuan ,  Yuxing Zhang

Inventor： Jianhua Zhao ,  Yuan Yuan ,  Yuxing Zhang

IPC: H03M1/66

CPC classification number: H03M1/685 ,  H03M1/765

Abstract: For high resolution resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row of the resistor string are fed into a multiplexer, wherein the multiplexer produces an output voltage. A method and apparatus are disclosed for implementing the reflective nature of Gray code to design a DAC such that all the switches in a column of the resistor string may be controlled with only one control signal, thereby reducing extra routing costs, surface area, and dynamic power consumed by the circuit.

Abstract translation: 对于高分辨率电阻串DAC，电阻串被放置在列和行的阵列中，每个电阻抽头连接到开关网络，并且解码器用于选择要闭合的开关，使得子DAC电压来自 电阻抽头连接到选定的开关。 电阻串的每行的电压被馈送到多路复用器中，其中多路复用器产生输出电压。 公开了一种用于实现格雷码的反射特性以设计DAC的方法和装置，使得可以仅使用一个控制信号来控制电阻串的列中的所有开关，从而降低额外的布线成本，表面积和动态 电路消耗的功率。

公开(公告)号：US20120032828A1

公开(公告)日：2012-02-09

申请号：US12965651

申请日：2010-12-10

Applicant: Jian Hua Zhao ,  Shawn Wang

Inventor： Jian Hua Zhao ,  Shawn Wang

IPC: H03M1/00 ,  H03M1/66

CPC classification number: H03M1/682 ,  H03M1/765

Abstract: For coarse resistor string DACs, a resistor string is placed in an array of columns and rows, each resistor tap is connected to a switch network, and a decoder is used to select switches to be closed such that sub-DAC voltage comes from the resistor taps connected to the selected switches. The voltages from each row are fed into multiplexers, wherein the multiplexers produce output voltages. DAC circuit designs extend the resolution of the output voltages by feeding them into a voltage interpolation amplifier. A method and apparatus are disclosed for implementing Gray code to design coarse DAC architecture for voltage interpolation such that the number of switches required by the circuit is significantly reduced, thereby decreasing required surface area, and improving glitch performance without increasing design complexity.

Abstract translation: 对于粗电阻串DAC，电阻串被放置在列和行的阵列中，每个电阻抽头连接到开关网络，并且解码器用于选择要闭合的开关，使得副DAC电压来自电阻器 抽头连接到选定的开关。 来自每行的电压被馈送到多路复用器中，其中多路复用器产生输出电压。 DAC电路设计通过将输出电压馈入电压内插放大器来扩展输出电压的分辨率。 公开了一种用于实现格雷码来设计用于电压内插的粗DAC架构的方法和装置，使得电路所需的开关数量显着减少，从而减少所需的表面积，并且在不增加设计复杂性的情况下改善毛刺性能。

公开(公告)号：US20110156763A1

公开(公告)日：2011-06-30

申请号：US12968633

申请日：2010-12-15

Applicant: Sarah GAO ,  Jianhua ZHAO ,  Wadeo OU

Inventor： Sarah GAO ,  Jianhua ZHAO ,  Wadeo OU

IPC: H03B1/00

CPC classification number: H04N5/232 ,  G02B7/08

Abstract: An embodiment of a circuit for driving an under-damped system comprises first and second signal generators. The first generator is operable to generate a first drive signal. And the second generator is operable to receive the first drive signal and a second drive signal, and to generate from the first and second drive signals a system drive signal having a first amplitude for a first duration and having a second amplitude after the first duration, the system drive signal operable to cause the under-damped system to operate in a substantially damped manner. Either or both of the first and second generators may be programmable such that one may adjust the response of any under-damped system by generating an appropriate drive signal instead of by physically modifying the system itself. In another embodiment, an under-damped system is caused to oscillate at a damped frequency having a first phase, and is also caused to oscillate at substantially the damped frequency having a second phase such that the oscillation at the first phase substantially cancels the oscillation at the second phase. Such embodiments may allow one to realize a faster settling time without slowing down the response time of an under-damped system.

Abstract translation: 用于驱动欠阻尼系统的电路的实施例包括第一和第二信号发生器。 第一发生器可操作以产生第一驱动信号。 并且第二发生器可操作以接收第一驱动信号和第二驱动信号，并且从第一和第二驱动信号产生具有第一持续时间的第一幅度并且在第一持续时间之后具有第二幅度的系统驱动信号， 系统驱动信号可操作以使欠阻尼系统以基本上阻尼的方式工作。 第一和第二发生器中的任一个或两者可以是可编程的，使得可以通过生成适当的驱动信号而不是通过物理地修改系统本身来调节任何欠阻尼系统的响应。 在另一个实施例中，使欠阻尼系统以具有第一相位的阻尼频率振荡，并且还使得基本上具有第二相位的阻尼频率振荡，使得第一相位的振荡基本上抵消了 第二阶段 这样的实施例可以允许人们实现更快的建立时间，而不会减缓欠阻尼系统的响应时间。

公开(公告)号：US20110075308A1

公开(公告)日：2011-03-31

申请号：US12892726

申请日：2010-09-28

Applicant: Zhaoang Yang ,  Haiyang Liu ,  Zhongxuan Tu ,  Jianxin Zhang

Inventor： Zhaoang Yang ,  Haiyang Liu ,  Zhongxuan Tu ,  Jianxin Zhang

IPC: H02H3/00

CPC classification number: G06K7/0013

Abstract: In one embodiment, a system for providing short circuit protection is disclosed. The system has a supply circuit and a series switch. The supply circuit has a supply input and a supply output, and is configured to deliver an output current at the supply output, and to disable the supply output if the output current exceeds a first current limit. The series switch coupled between the supply output of the supply circuit and a supply node, and the supply node is configured to be coupled to a load.

Abstract translation: 在一个实施例中，公开了一种用于提供短路保护的系统。 该系统具有电源电路和串联开关。 供电电路具有电源输入和电源输出，并且被配置为在电源输出端传送输出电流，并且如果输出电流超过第一电流限制，则禁止电源输出。 耦合在电源电路的电源输出和供电节点之间的串联开关和供电节点被配置为耦合到负载。

公开(公告)号：US20110074328A1

公开(公告)日：2011-03-31

申请号：US12892500

申请日：2010-09-28

Applicant: Zhongrui "Kevin" Zhao

Inventor： Zhongrui "Kevin" Zhao

IPC: H02H7/085

CPC classification number: H02K11/001 ,  B60L3/0061 ,  B60L2200/12 ,  H02H7/0838 ,  H02K11/20

Abstract: In one embodiment, a system for controlling a motor is disclosed. The system has a driver circuit configured to drive a motor, a current sensing impedance coupled to the driver circuit, and an overload detection circuit coupled to the current sending impedance that has a transistor and a detection output node.

Abstract translation: 在一个实施例中，公开了一种用于控制电动机的系统。 该系统具有被配置为驱动电动机的驱动器电路，耦合到驱动器电路的电流感测阻抗以及耦合到具有晶体管和检测输出节点的电流发送阻抗的过载检测电路。

公开(公告)号：US09000811B2

公开(公告)日：2015-04-07

申请号：US14199313

申请日：2014-03-06

Applicant: STMicroelectronics R&D (Shanghai) Co. Ltd.

Inventor： Fei Wang ,  Wen Li Bai

IPC: H03K3/00 ,  H03K17/04 ,  H03K17/00

CPC classification number: H03K17/00 ,  H03K17/163

Abstract: The gate of a drive transistor having a drain and source is discharged by a circuit including a sensing circuit configured to sense a drain-to-source voltage of the drive transistor. A first current sink path is coupled to the gate of the drive transistor. The first current sink path applies a high discharge current to the gate of the drive transistor when the sensing current senses a lower drain-to-source voltage of the drive transistor. A second current sink path is also coupled to the gate of the drive transistor. The second current sink path is configured to apply a low discharge current to the gate of the drive transistor when the sensing current senses a higher drain-to-source voltage of the drive transistor.

Abstract translation: 具有漏极和源极的驱动晶体管的栅极由包括感测电路的电路放电，该感测电路被配置为感测驱动晶体管的漏极 - 源极电压。 第一电流吸收通路耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较低的漏极 - 源极电压时，第一电流阱路径向驱动晶体管的栅极施加高放电电流。 第二电流吸收通路也耦合到驱动晶体管的栅极。 当感测电流感测到驱动晶体管的较高的漏极 - 源极电压时，第二电流吸收通道被配置为向驱动晶体管的栅极施加低放电电流。

公开(公告)号：US08854119B2

公开(公告)日：2014-10-07

申请号：US13924775

申请日：2013-06-24

Applicant: STMicroelectronics R&D Co. Ltd. (Shanghai)

Inventor： Ming Jiang ,  Jackson Ding

IPC: H02M3/07

CPC classification number: H02M3/07 ,  H02M2003/078

Abstract: A circuit includes a charge pump, a first level shifter, a second level shifter, a voltage follower and a current mirror. The charge pump is configured to generate a voltage difference between the input node and the output node. The first level shifter is coupled to the charge pump output and configured to apply a first voltage variation to the charge pump output in response to a bias current. The second level shifter is coupled to the input node and configured to apply a second voltage variation to the charge pump input. The voltage follower is configured to equalize outputs from the first and second level shifters and provide a difference current which is multiplied by the current multiplier to generate a charging current applied to the charge pump.

Abstract translation: 电路包括电荷泵，第一电平移位器，第二电平移位器，电压跟随器和电流镜。 电荷泵被配置为在输入节点和输出节点之间产生电压差。 第一电平移位器耦合到电荷泵输出并被配置为响应偏置电流向电荷泵输出施加第一电压变化。 第二电平移位器耦合到输入节点并被配置为向电荷泵输入施加第二电压变化。 电压跟随器被配置为对来自第一和第二电平移位器的输出进行均衡，并提供与电流乘法器相乘的差电流，以产生施加到电荷泵的充电电流。