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公开(公告)号：US20230377905A1
公开(公告)日：2023-11-23
申请号：US17751234
申请日：2022-05-23
发明人： Chien-Li Kuo , Chien-Chen Li , Kuo-Chio Liu , Kuang-Chun Lee , Wen-Yi Lin
IPC分类号： H01L21/48 , H01L23/48 , H01L23/31 , H01L23/498 , H01L23/538 , H01L23/00
CPC分类号： H01L21/486 , H01L23/481 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/73 , H01L2224/04105 , H01L2224/12105 , H01L2924/15311 , H01L2224/73267
摘要： In an embodiment, a device includes: an integrated circuit die including a die connector; a first through via adjacent the integrated circuit die; an encapsulant encapsulating the first through via and the integrated circuit die; and a redistribution structure on the encapsulant, the redistribution structure including a redistribution line, the redistribution line physically and electrically coupled to the die connector of the integrated circuit die, the redistribution line electrically isolated from the first through via, the redistribution line crossing over the first through via.
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公开(公告)号：US20240365461A1
公开(公告)日：2024-10-31
申请号：US18769912
申请日：2024-07-11
发明人： Yu-Kuang SUN , Ming-Hsun TSAI , Wei-Shin CHENG , Cheng-Hao LAI , Hsin-Feng CHEN , Chiao-Hua CHENG , Cheng-Hsuan WU , Yu-Fa LO , Jou-Hsuan LU , Shang-Chieh CHIEN , Li-Jui CHEN , Heng-Hsin LIU
CPC分类号： H05G2/006 , G03F7/70033 , G05D23/19
摘要： The present disclosure is directed to a modularized vessel droplet generator assembly (MGDVA) including a droplet generator assembly (DGA). Under a normal operation, the liquid fuel moves along an operation pathway extending through the DGA to eject or discharge the liquid fuel (e.g., liquid tin) from a nozzle of the DGA into a vacuum chamber. The liquid fuel in the vacuum chamber is then exposed to a laser generating an extreme ultra-violet (EUV) light. Under a service operation, the operation pathway is closed and a service pathway extending through the DGA is opened. A gas is introduced into the service pathway forming a gas-liquid interface between the gas and the liquid fuel. The gas-liquid interface is driven to an isolation valve directly adjacent to the DGA. In other words, the gas pushes back the liquid fuel to the isolation valve. Once the gas-liquid interface reaches the isolation valve, the isolation valve is closed isolating the DGA from the liquid fuel.
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公开(公告)号：US20240363757A1
公开(公告)日：2024-10-31
申请号：US18770865
申请日：2024-07-12
发明人： Li-Zhen Yu , Jia-Chuan You , Chia-Hao Chang , Tien-Lu Lin , Yu-Ming Lin , Chih-Hao Wang
IPC分类号： H01L29/78 , H01L21/02 , H01L27/088 , H01L29/66
CPC分类号： H01L29/7851 , H01L21/02381 , H01L21/02532 , H01L27/0886 , H01L29/66795 , H01L29/7848
摘要： A method includes providing a semiconductor structure having metal gate structures (MGs), gate spacers disposed on sidewalls of the MGs, and source/drain (S/D) features disposed adjacent to the gate spacers; forming a first dielectric layer over the MGs and forming S/D contacts (MDs) over the S/D features; forming a second dielectric layer over the first dielectric layer, where portions of the second dielectric layer contact the MDs and the second dielectric layer is different from the first dielectric layer in composition; removing the portions of the second dielectric layer that contact the MDs; forming a conductive layer over the MDs and over the first dielectric layer; and removing portions of the conductive layer to form conductive features over the MDs.
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4.发明公开公开(公告)号：US20240363752A1
公开(公告)日：2024-10-31
申请号：US18766402
申请日：2024-07-08
发明人： Yi-Sin WANG , Shan-Yun CHENG , Ching-Hung KAO , Jing-Jyu CHOU , Yi-Ting CHEN
IPC分类号： H01L29/78 , H01L21/762 , H01L21/8238 , H01L27/092 , H01L29/267 , H01L29/66
CPC分类号： H01L29/7848 , H01L21/76224 , H01L21/823814 , H01L21/823878 , H01L27/092 , H01L29/267 , H01L29/66545
摘要： A method and apparatus for minimizing silicon germanium facets in planar metal oxide semiconductor structures is disclosed. For example, a device fabricated according to the method may include a semiconductor substrate, a plurality of gate stacks formed on the substrate, a plurality of source/drain regions formed from silicon germanium, and a shallow trench isolation region positioned between two source/drain regions of the plurality of source/drain regions. Each source/drain region of the plurality of source/drain regions is positioned adjacent to at least one gate stack of the plurality of gate stacks. Moreover, the shallow trench isolation region forms a trench in the substrate without intersecting the two source/drain regions.
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公开(公告)号：US20240363734A1
公开(公告)日：2024-10-31
申请号：US18770088
申请日：2024-07-11
发明人： Ru-Shang Hsiao , Ching-Hwanq Su , Pin Chia Su , Ying Hsin Lu , Ling-Sung Wang
IPC分类号： H01L29/66 , H01L21/28 , H01L21/762 , H01L21/768 , H01L21/8234 , H01L29/08 , H01L29/49 , H01L29/78
CPC分类号： H01L29/66795 , H01L21/28088 , H01L21/76877 , H01L21/82345 , H01L29/0847 , H01L29/4966 , H01L29/66545 , H01L29/785 , H01L29/7851 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823437 , H01L21/823481
摘要： A method includes forming a dummy gate stack over a semiconductor region, removing the dummy gate stack to form a trench between gate spacers, forming a replacement gate dielectric extending into the trench, and forming a replacement gate electrode on the replacement gate dielectric. The forming the replacement gate electrode includes depositing a metal-containing layer. The depositing the metal-containing layer includes depositing a lower layer having a first average grain size, and depositing an upper layer over the lower layer. The lower layer and the upper layer are formed of a same material, and the upper layer has a second average grain size greater than the first average grain size. Source and drain regions are formed on opposing sides of the replacement gate electrode.
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公开(公告)号：US20240363719A1
公开(公告)日：2024-10-31
申请号：US18770040
申请日：2024-07-11
发明人： Hsin-Yi Lee , Hsuan-Yu Tung , Chin-You Hsu , Cheng-Lung Hung
IPC分类号： H01L29/49 , H01L21/28 , H01L21/8234 , H01L27/088 , H01L29/06 , H01L29/66 , H01L29/78
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/28247 , H01L21/823431 , H01L21/82345 , H01L21/823468 , H01L27/0886 , H01L29/0649 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： Semiconductor devices and methods of manufacturing semiconductor devices are provided. In embodiments a passivation process is utilized in order to reduce dangling bonds and defects within work function layers within a gate stack. The passivation process introduces a passivating element which will react with the dangling bonds to passivate the dangling bonds. Additionally, in some embodiments the passivating elements will trap other elements and reduce or prevent them from diffusing into other portions of the structure.
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公开(公告)号：US20240363718A1
公开(公告)日：2024-10-31
申请号：US18767174
申请日：2024-07-09
发明人： Hsin-Yi Lee , Cheng-Lung Hung , Chi On Chui
IPC分类号： H01L29/49 , H01L21/285 , H01L21/8234 , H01L29/40 , H01L29/78
CPC分类号： H01L29/4966 , H01L21/28568 , H01L21/82345 , H01L29/401 , H01L29/785
摘要： A method includes forming a gate dielectric layer on a semiconductor region, and depositing a first aluminum-containing work function layer using a first aluminum-containing precursor. The first aluminum-containing work function layer is over the gate dielectric layer. A second aluminum-containing work function layer is deposited using a second aluminum-containing precursor, which is different from the first aluminum-containing precursor. The second aluminum-containing work function layer is deposited over the first aluminum-containing work function layer. A conductive region is formed over the second aluminum-containing work function layer.
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8.发明公开公开(公告)号：US20240363713A1
公开(公告)日：2024-10-31
申请号：US18766767
申请日：2024-07-09
发明人： Tsai-Jung Ho , Tze-Liang Lee
IPC分类号： H01L29/423 , H01L21/8234 , H01L29/66 , H01L29/786
CPC分类号： H01L29/42392 , H01L21/823418 , H01L21/823468 , H01L29/66545 , H01L29/6656 , H01L29/78618
摘要： A device includes a substrate including an active region, a gate stack over the active region, and a hard mask over the gate stack. The hard mask includes a capping layer, a buttress layer extending along sidewalls and a bottom of the capping layer, and a liner layer extending along sidewalls and a bottom of the buttress layer. The buttress layer includes a metal oxide material or a metal nitride material.
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9.发明公开公开(公告)号：US20240363709A1
公开(公告)日：2024-10-31
申请号：US18770563
申请日：2024-07-11
发明人： Lin-Yu Huang , Li-Zhen Yu , Chia-Hao Chang , Cheng-Chi Chuang , Kuan-Lun Cheng , Chih-Hao Wang
IPC分类号： H01L29/417 , H01L21/768 , H01L23/522 , H01L29/08 , H01L29/78
CPC分类号： H01L29/41791 , H01L21/76877 , H01L23/5226 , H01L29/0847 , H01L29/785
摘要： A semiconductor structure includes a substrate; a first structure over the substrate and having a first gate stack and two first gate spacers on two opposing sidewalls of the first gate stack; a second structure over the substrate and having a second gate stack and two second gate spacers on two opposing sidewalls of the second gate stack; a source/drain (S/D) feature over the substrate and adjacent to the first and the second gate stacks; an S/D contact over the S/D feature and between one of the first gate spacers and one of the second gate spacers; a conductive via disposed over and electrically connected to the S/D contact; and a dielectric liner layer. A first portion of the dielectric liner layer is disposed on a sidewall of the one of the first gate spacers and is directly above the S/D contact and spaced from the S/D contact.
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10.发明公开公开(公告)号：US20240363658A1
公开(公告)日：2024-10-31
申请号：US18770566
申请日：2024-07-11
发明人： Chih-Yu TSENG , Ming-Hsien CHEN
IPC分类号： H01L27/146 , H04N25/53 , H04N25/709 , H04N25/71 , H04N25/711 , H04N25/75 , H04N25/771
CPC分类号： H01L27/14623 , H01L27/14612 , H01L27/14636 , H01L27/14643 , H01L27/14685 , H01L27/14689 , H04N25/53 , H04N25/711 , H04N25/771 , H04N25/709 , H04N25/745 , H04N25/75
摘要： Disclosed is a CMOS image sensor with global shutters and a method for fabricating the CMOS image sensor. In one embodiment, a semiconductor device, includes: a light-sensing region; a charge-storage region; a light-shielding structure; and at least one via contact; wherein the charge-storage region is spatially configured adjacent to the light-sensing region in a lateral direction, wherein the light-shielding structure is configured over the charge-storage region in a vertical direction so as to prevent incident light leaking from the light-sensing region to the signal-processing region, wherein the light-shielding structure is configured in an interlayer dielectric (ILD) layer, and wherein the light-shielding structure is simultaneously formed with the at least one via contact.
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