Mask transfer method (and related apparatus) for a bumping process

    公开(公告)号:US12132039B2

    公开(公告)日:2024-10-29

    申请号:US18332069

    申请日:2023-06-09

    IPC分类号: H01L33/00 H01L25/16 H01L33/62

    摘要: Various embodiments of the present disclosure are directed towards an integrated chip (IC). The IC includes a first dielectric structure having first inner sidewalls over an interlayer dielectric (ILD) structure. A second dielectric structure is over the first dielectric structure, where the first inner sidewalls are between second inner sidewalls of the second dielectric structure. A sidewall barrier structure is over the first dielectric structure and extends vertically along the second inner sidewalls. A lower bumping structure is between the second inner sidewalls and extends vertically along the first inner sidewalls and vertically along third inner sidewalls of the sidewall barrier structure. An upper bumping structure is over both the lower bumping structure and the sidewall barrier structure and between the second inner sidewalls, where an uppermost point of the upper bumping structure is at or below an uppermost point of the second dielectric structure.

    Hierarchical dictionary with statistical filtering based on word frequency

    公开(公告)号:US12130854B2

    公开(公告)日:2024-10-29

    申请号:US17175254

    申请日:2021-02-12

    摘要: A hierarchical dictionary having methods of storing words based on frequency thereof in one or more documents which includes the steps of identifying a hash value corresponding to an inputted word; storing the word in a first hash map and in a second hash map having a substantially larger word storage capacity than the first hash map based on the identified hash value; clearing the first hash map at every predetermined period or triggering event; determining whether a frequency of the word as stored in the second hash map exceeds a predetermined value; and if so, promoting the word from the second hash map to a third hash map having a substantially larger word storage capacity than the second hash map for long-term storage and later retrieval.

    Ferroelectric random access memory device with seed layer

    公开(公告)号:US12069867B2

    公开(公告)日:2024-08-20

    申请号:US17843236

    申请日:2022-06-17

    IPC分类号: H01L21/00 H01L49/02 H10B53/30

    CPC分类号: H10B53/30 H01L28/56 H01L28/60

    摘要: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a bottom electrode layer over a substrate and forming a seed layer over the bottom electrode layer. A ferroelectric switching layer is formed over the bottom electrode layer and to contact the seed layer. The ferroelectric switching layer is formed to have a first region with a first crystal phase and a second region with a different crystal phase. A top electrode layer is formed over the ferroelectric switching layer. One or more patterning processes are performed on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a ferroelectric random access memory (FeRAM) device.