公开(公告)号：US08437184B1

公开(公告)日：2013-05-07

申请号：US13312074

申请日：2011-12-06

申请人： Chih-Wei Hsiung

发明人： Chih-Wei Hsiung

IPC分类号： G11C11/34

CPC分类号： H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： A method of controlling a vertical dual-gate DRAM provides a short circuit state, a clearing state and a false broken circuit state. In the short circuit state, a first gate and a second gate at two sides of a first pillar are controlled to respectively have a turn-on voltage to form electric connection between a drain and a source at two ends of the first pillar. In the clearing state, the first gate and second gate are controlled to respectively have a clearing voltage to disconnect electric connection between the drain and source at two ends of the first pillar. The false broken circuit state is entered after the clearing state has been finished. The invention does not separate gates between neighboring pillars, but controls ON/OFF of transistors electrically so that no current leakage is generated in the clearing state and problem of inaccurate data reading can be prevented.

摘要翻译： 控制垂直双栅极DRAM的方法提供短路状态，清零状态和假断路状态。 在短路状态下，控制第一支柱两侧的第一栅极和第二栅极分别具有导通电压，以在第一支柱的两端形成漏极与源极之间的电连接。 在清除状态下，控制第一栅极和第二栅极分别具有清除电压，以在第一支柱的两端断开漏极和源极之间的电连接。 在清除状态结束后进入错误的断路状态。 本发明不在相邻柱之间分隔栅极，而是电连接晶体管的导通/截止，从而在清除状态下不产生电流泄漏，并且可以防止数据读取不准确的问题。