公开(公告)号：US08383952B2

公开(公告)日：2013-02-26

申请号：US12851014

申请日：2010-08-05

申请人： Zhigang Wang ,  Vivek Subramanian ,  Lee Cleveland

发明人： Zhigang Wang ,  Vivek Subramanian ,  Lee Cleveland

IPC分类号： H05K1/00 ,  H05K3/12 ,  G06F17/50

CPC分类号： H05K3/0085 ,  G11C14/0054 ,  G11C17/14 ,  G11C17/18 ,  H01L23/5328 ,  H01L51/0022 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0296 ,  H05K1/16 ,  H05K3/125 ,  H05K2201/09245 ,  Y10T29/49155 ,  H01L2924/00

摘要： Embodiments of the present invention relate to circuit layouts that are compatible with printing electronic inks, printed circuits formed by printing an electronic ink or a combination of printing and conventional blanket deposition and photolithography, and methods of forming circuits by printing electronic inks onto structures having print-compatible shapes. The layouts include features having (i) a print-compatible shape and (ii) an orientation that is either orthogonal or parallel to the orientation of every other feature in the layout.

摘要翻译： 本发明的实施例涉及与打印电子墨水，通过印刷电子墨水或印刷和常规覆盖层沉积和光刻的组合形成的印刷电路的电路布局，以及通过将电子墨水印刷到具有印刷的结构上形成电路的方法 兼容的形状。 布局包括具有（i）打印兼容形状和（ii）与布局中的每个其他特征的取向正交或平行的取向的特征。

公开(公告)号：US08370786B1

公开(公告)日：2013-02-05

申请号：US13149275

申请日：2011-05-31

申请人： Michael Burstein

发明人： Michael Burstein

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/84

摘要： Methods and software for placing or re-placing integrated circuit cells and routing or re-routing nets between the cells in an integrated circuit layout. The method includes selecting a region of the cells in the integrated circuit layout, selecting a cell within the selected region, locating a border point where a net coupled to the selected cell crosses a border of the selected region, and moving the selected cell within the selected region to improve a timing characteristic (e.g., a wire length, capacitance, or other characteristic of the net that affects timing or delay) of the net. The method and software advantageously improve the placement of cells and routing of wires around congested or reserved regions after global routing has been performed, without causing timing violations in other signal paths on the integrated circuit device, in a computationally efficient manner.

摘要翻译： 用于在集成电路布局中放置或重新放置集成电路单元和在单元之间布线或重新布线网络的方法和软件。 该方法包括选择集成电路布局中的单元的区域，选择所选区域内的单元，定位耦合到所选单元的网跨越所选区域的边界的边界点，以及移动所选区域内的所选单元 以改善网络的定时特性（例如，网线的长度，电容或其他影响时序或延迟的特性）。 该方法和软件有利地在计算上有效的方式改善了在全局路由已经执行之后，在集线电路设备上的其他信号路径中不引起定时违反的情况下，在拥塞或保留区域周围的线路的布置以及布线。

公开(公告)号：US08293612B2

公开(公告)日：2012-10-23

申请号：US12494028

申请日：2009-06-29

申请人： Yong Jun Lee

发明人： Yong Jun Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7835 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/0653 ,  H01L29/66659

摘要： A method for manufacturing a lateral double diffused metal oxide semiconductor (LDMOS) device includes forming an oxide layer on a semiconductor substrate, forming first and second trenches by partially etching the oxide layer and the semiconductor substrate, forming a small trench overlapping with the second trench so that the second trench has a stepped structure, and depositing one or more dielectric layers so that the first trench forms a device isolation layer defining a semiconductor device region and the second trench having a stepped structure forms a drain extension device isolation layer. The breakdown voltage of the LDMOS device may be improved while reducing the on-resistance, thereby improving the operational reliability of the device.

摘要翻译： 制造横向双重扩散金属氧化物半导体（LDMOS）器件的方法包括在半导体衬底上形成氧化物层，通过部分蚀刻氧化物层和半导体衬底形成第一和第二沟槽，形成与第二沟槽重叠的小沟槽 使得第二沟槽具有阶梯结构，并且沉积一个或多个电介质层，使得第一沟槽形成限定半导体器件区域的器件隔离层，并且具有阶梯结构的第二沟槽形成漏极延伸器件隔离层。 可以在降低导通电阻的同时提高LDMOS器件的击穿电压，从而提高器件的工作可靠性。

公开(公告)号：US08269909B2

公开(公告)日：2012-09-18

申请号：US12643781

申请日：2009-12-21

申请人： Nam Chil Moon

发明人： Nam Chil Moon

IPC分类号： G02F1/136

CPC分类号： G02F1/1365 ,  G02F2203/01

摘要： Disclosed is a method for fabrication of a liquid crystal display with improved optical transmission, which includes sequentially forming a first oxide film, a silicon film, and a second oxide film on a semiconductor substrate, selectively etching the silicon film and the second oxide film to expose the first oxide film, forming a oxynitride film on at least the silicon film, forming a polysilicon layer over the oxynitride film, selectively etching the polysilicon layer to form a top electrode, forming an insulating film on and/or over the substrate, including the top electrode, and forming metal wirings on outer regions of the top electrode.

摘要翻译： 公开了一种用于制造具有改进的光传输的液晶显示器的方法，其包括在半导体衬底上依次形成第一氧化物膜，硅膜和第二氧化物膜，选择性地将硅膜和第二氧化物膜蚀刻到 暴露第一氧化物膜，在至少硅膜上形成氧氮化物膜，在氧氮化物膜上形成多晶硅层，选择性地蚀刻多晶硅层以形成顶部电极，在基板上和/或上方形成绝缘膜，包括 顶部电极，以及在顶部电极的外部区域上形成金属布线。

公开(公告)号：US08202757B2

公开(公告)日：2012-06-19

申请号：US12501341

申请日：2009-07-10

申请人： Chang Hun Han

发明人： Chang Hun Han

IPC分类号： H01L21/00 ,  H01L21/44 ,  H01L21/311 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/14634 ,  H01L27/14603

摘要： An image sensor includes readout circuitry on a first substrate, a metal line electrically connected with the readout circuitry, a dielectric on the metal line, an image sensing device on the dielectric, including first and second conductivity type layers, a contact plug in a via hole penetrating the image sensing device to connect the first conductivity type layer with the metal line, and a sidewall dielectric in the via hole at a sidewall of the second conductivity type layer.

摘要翻译： 图像传感器包括在第一基板上的读出电路，与读出电路电连接的金属线，金属线上的电介质，介质上的图像感测装置，包括第一和第二导电类型的层， 穿过图像感测装置的孔，以将第一导电类型层与金属线连接，以及在第二导电类型层的侧壁处的通孔中的侧壁电介质。

公开(公告)号：US08178441B2

公开(公告)日：2012-05-15

申请号：US11186396

申请日：2005-07-21

申请人： Seok-Su Kim

发明人： Seok-Su Kim

IPC分类号： H01L21/44 ,  H01L21/4763

CPC分类号： H01L21/76802 ,  H01L21/28525 ,  H01L21/76801 ,  H01L21/76837 ,  H01L21/823425

摘要： A method for manufacturing a semiconductor device includes forming a gate insulating layer, a gate and a protective layer on a semiconductor substrate, forming a spacer on lateral sides of the protective layer and the gate, forming one or more junction regions in the semiconductor substrate at sides of the gate, partially filling a gap between adjacent gates by selectively forming a conductive layer on an exposed portion of the semiconductor substrate between the adjacent gates, forming an insulating layer over the semiconductor substrate so as to fill a full height of the gap between the adjacent gates, and forming a contact hole partially exposing the conductive layer by etching the insulating layer.

摘要翻译： 一种半导体器件的制造方法包括在半导体衬底上形成栅极绝缘层，栅极和保护层，在保护层和栅极的侧面形成间隔物，在半导体衬底中形成一个或多个结区域 通过在相邻栅极之间的半导体衬底的暴露部分上选择性地形成导电层，在相邻栅极之间部分地填充间隙，在半导体衬底上形成绝缘层，以便填充半导体衬底之间的间隙的全高 并且通过蚀刻绝缘层形成部分暴露导电层的接触孔。

公开(公告)号：US08173457B2

公开(公告)日：2012-05-08

申请号：US13056971

申请日：2009-08-03

申请人： Hyung Sup Lee

发明人： Hyung Sup Lee

IPC分类号： H01L21/00

CPC分类号： H01L27/124 ,  G02F1/1368 ,  H01L27/1288

摘要： A method and apparatus of fabricating a thin film transistor array substrate is disclosed, which is capable of reducing fabrication time owing to a simplified fabrication process, wherein at least one of steps for forming a gate pattern, forming a semiconductor pattern, forming a data pattern, removing an ohmic contact layer pattern exposed between source and drain electrode patterns, and forming a conductive layer pattern is performed by a laser scribing process.

摘要翻译： 公开了一种制造薄膜晶体管阵列基板的方法和装置，其能够由于简化的制造工艺而缩短制造时间，其中至少一个步骤用于形成栅极图案，形成半导体图案，形成数据图案 通过激光划线工艺来去除在源电极图案和漏电极图案之间暴露的欧姆接触层图案，以及形成导电层图案。

公开(公告)号：US08159077B2

公开(公告)日：2012-04-17

申请号：US12276195

申请日：2008-11-21

申请人： Sung Su Kim

发明人： Sung Su Kim

IPC分类号： H01L29/40

CPC分类号： H01G4/38 ,  H01G4/30 ,  H01L23/5223 ,  H01L23/5227 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05093 ,  H01L2224/05096 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/30107

摘要： A pad in a semiconductor device and fabricating method thereof are disclosed. The pad includes an uppermost metal layer first to Nth intermediate metal layers, wherein capacitors configured or formed by the uppermost metal layer and the first to Nth intermediate metal layers are serially connected. Accordingly, the pad reduces total parasitic capacitance components by connecting MIM type capacitors in series, and not necessarily overlapping with each other, thereby minimizing design errors attributed to the pad by reducing parasitic factors generated from the integrated circuit design. The pad may also minimize capacitance attributed to resonance at a specific frequency. Moreover, the pad avoids affecting an adjacent pad or circuit without additional processing, despite maintaining the above-mentioned effects, thereby reducing cost.

摘要翻译： 公开了半导体器件中的焊盘及其制造方法。 焊盘包括第一至第N中间金属层的最上层金属层，其中由最上层的金属层和第一至第N中间金属层构成或形成的电容器串联连接。 因此，该焊盘通过串联连接MIM型电容器而减少总寄生电容分量，并且不一定彼此重叠，从而通过减少从集成电路设计产生的寄生因子来最小化归因于焊盘的设计误差。 衬垫还可以最小化在特定频率下由于谐振引起的电容。 此外，尽管保持了上述的效果，垫不避免附加处理影响相邻的焊盘或电路，从而降低了成本。

公开(公告)号：US08102017B2

公开(公告)日：2012-01-24

申请号：US12341864

申请日：2008-12-22

申请人： Ki Jun Yun

发明人： Ki Jun Yun

IPC分类号： H01L27/146

CPC分类号： H01L27/14665 ,  H01L27/14634

摘要： An image sensor may comprise circuitry, a first lower electrode, a photodiode, an upper electrode, a second lower electrode, and an upper interconnection. The circuitry may comprise a first lower interconnection and a second lower interconnection over a dielectric of a substrate. The first lower electrode, the photodiode, and the upper electrode may be sequentially formed over the first lower interconnection. The second lower electrode may comprise a passivation layer over the second lower interconnection. The upper interconnection may be formed over the second lower electrode and electrically connected to the upper electrode.

摘要翻译： 图像传感器可以包括电路，第一下电极，光电二极管，上电极，第二下电极和上互连。 电路可以包括第一下互连和在衬底的电介质上的第二下互连。 第一下电极，光电二极管和上电极可以顺序地形成在第一下互连上。 第二下电极可以包括在第二下互连上的钝化层。 上互连可以形成在第二下电极上并电连接到上电极。

公开(公告)号：US08099707B1

公开(公告)日：2012-01-17

申请号：US12405909

申请日：2009-03-17

申请人： Jiang Li

发明人： Jiang Li

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  H01L27/11803 ,  H03K19/17796

摘要： Semiconductor devices and/or structures, and methods for fabricating the same are disclosed. Embodiments of the present invention allow for production of customized products, while also minimizing production steps, avoiding some or all photolithography steps, and reducing overall production costs. Using selective deposition and patterning methods such as printing, to form metal and/or dielectric layer(s) on substrates where one or more device circuit components are pre-made in a factory, but which require further processing to obtain an electrically functional circuit, results in the ability for a user/consumer to make custom, specific and/or unique electrically functional circuits without incurring the cost and complexity of a full fabrication to form and pattern all of the layers.

摘要翻译： 公开了半导体器件和/或结构及其制造方法。 本发明的实施例允许定制产品的生产，同时最小化生产步骤，避免一些或所有光刻步骤，并降低整体生产成本。 使用诸如印刷的选择性沉积和图案化方法在基板上形成金属和/或介电层，其中一个或多个器件电路部件在工厂中预先制造，但需要进一步处理以获得电功能电路， 导致用户/消费者能够制造定制，特定和/或独特的电功能电路，而不会导致完整制造的成本和复杂性以形成和图案化所有层。