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    Apparatus for containment and concentration of volatile esters
    2.
    发明授权
    Apparatus for containment and concentration of volatile esters 失效
    用于容纳和浓缩挥发性酯的装置

    公开(公告)号：US08413841B2

    公开(公告)日：2013-04-09

    申请号：US11621112

    申请日：2007-01-08

    申请人： Randy Mark Cunningham

    发明人： Randy Mark Cunningham

    IPC分类号： B65D43/08

    CPC分类号： A47G19/2205 ,  A47G2400/045

    摘要： An apparatus and method are disclosed and pertain to a lid for use with a container having a rim and an opening where volatile esters from an aromatic compound are dispersing into the environment and for enhancing the identification of the volatile esters. The lid is comprised of a generally planar laterally stabilized gas restrictive material for decreasing the dispersion rate of the volatile esters, resulting in increased concentration of the volatile esters within the container and enhancing the identification of the volatile esters emitted from the aromatic compound. The lid includes a surface for coupling to the rim in a manner that laterally stabilizes the lid so that it remains sufficiently fixed to the rim during agitation of the container. The surface also permits the lid to be removed from the rim.

    摘要翻译： 公开了一种装置和方法，其与具有边缘和开口的容器一起使用，其中来自芳族化合物的挥发性酯分散到环境中并用于增强挥发性酯的鉴定。 该盖由用于降低挥发性酯的分散速率的大致平面的横向稳定的气体限制材料构成，导致容器内挥发性酯的浓度增加并且增强了从芳族化合物发出的挥发性酯的鉴定。 盖子包括用于以使横向稳定盖子的方式联接到轮辋的表面，使得在搅拌容器期间它保持足够的固定到轮辋上。 表面也允许盖子从边缘移除。

    Hybrid multi-tiered caching storage system
    3.
    发明授权
    Hybrid multi-tiered caching storage system 有权
    混合多层缓存存储系统

    公开(公告)号：US08032700B2

    公开(公告)日：2011-10-04

    申请号：US12575480

    申请日：2009-10-08

    申请人： Rey H. Bruce ,  Noeme P. Mateo ,  Ricky S. Nite

    发明人： Rey H. Bruce ,  Noeme P. Mateo ,  Ricky S. Nite

    IPC分类号： G06F12/00

    CPC分类号： G06F13/28 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0685 ,  G06F12/0866 ,  G06F12/0897 ,  G06F2212/2022 ,  G06F2212/217

    摘要： A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.

    摘要翻译： 描述了包括机械盘驱动装置，闪存装置，SDRAM存储装置和SRAM存储装置的混合存储系统。 IO处理器装置和DMA控制器装置被设计为消除主机干预。 多层缓存系统和用于将逻辑地址映射到物理地址的新颖数据结构导致可配置和可扩展的高性能计算机数据存储解决方案。

    Hybrid multi-tiered caching storage system
    5.
    发明授权
    Hybrid multi-tiered caching storage system 有权
    混合多层缓存存储系统

    公开(公告)号：US07613876B2

    公开(公告)日：2009-11-03

    申请号：US11450023

    申请日：2006-06-08

    申请人： Rey H. Bruce ,  Noeme Paz Mateo ,  Ricky Sevilla Nite

    发明人： Rey H. Bruce ,  Noeme Paz Mateo ,  Ricky Sevilla Nite

    IPC分类号： G06F12/00

    CPC分类号： G06F13/28 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0685 ,  G06F12/0866 ,  G06F12/0897 ,  G06F2212/2022 ,  G06F2212/217

    摘要： A hybrid storage system comprising mechanical disk drive means, flash memory means, SDRAM memory means, and SRAM memory means is described. IO processor means and DMA controller means are devised to eliminate host intervention. Multi-tiered caching system and novel data structure for mapping logical address to physical address results in a configurable and scalable high performance computer data storage solution.

    摘要翻译： 描述了包括机械盘驱动装置，闪存装置，SDRAM存储装置和SRAM存储装置的混合存储系统。 IO处理器装置和DMA控制器装置被设计为消除主机干预。 多层缓存系统和用于将逻辑地址映射到物理地址的新颖数据结构导致可配置和可扩展的高性能计算机数据存储解决方案。

    Multi pulse linear ionizer
    6.
    发明授权
    Multi pulse linear ionizer 有权
    多脉冲线性离子发生器

    公开(公告)号：US08773837B2

    公开(公告)日：2014-07-08

    申请号：US13367369

    申请日：2012-02-06

    申请人： Leslie Partridge ,  Peter Gefter ,  Edward Oldynski

    发明人： Leslie Partridge ,  Peter Gefter ,  Edward Oldynski

    IPC分类号： H01T23/00

    CPC分类号： H01T23/00

    摘要： An embodiment of the invention provides a method for generating ions within a space separating an emitter and a reference electrode, the method comprising: generating a variable number of small sharp pulses and rate of the pulses depending on the distance of the target from the emitter.

    摘要翻译： 本发明的实施例提供了一种在分离发射器和参考电极的空间内产生离子的方法，该方法包括：根据靶与发射极的距离，产生可变数量的小锐利脉冲和脉冲速率。

    Input-output device and storage controller handshake protocol using key exchange for data security
    8.
    发明授权
    Input-output device and storage controller handshake protocol using key exchange for data security 有权
    输入输出设备和存储控制器握手协议，使用密钥交换进行数据安全

    公开(公告)号：US08165301B1

    公开(公告)日：2012-04-24

    申请号：US11398321

    申请日：2006-04-04

    申请人： Rey Bruce ,  Marizonne Operio Fuentes ,  Raquel Bautista David

    发明人： Rey Bruce ,  Marizonne Operio Fuentes ,  Raquel Bautista David

    IPC分类号： H04L9/06

    CPC分类号： H04L9/0894 ,  G06F21/82 ,  H04L9/0822

    摘要： A protocol for providing secured IO device and storage controller handshake protocol; IO device controlled cipher settings, and secured data storage and access in memory. An IO device requesting data transfer with encryption and/or decryption, requests session keys from the processor. The processor generates a fresh public-private key pair for the session. The public key is sent to the requesting IO device; the private key is momentarily saved by the processor for the session. The requesting IO device generates a secret key and its desired cipher setting; furthermore, encrypts the secret key and cipher setting using the public key, and sends secret key and cipher setting to the processor. The processor uses the private key to decrypt the secret key and cipher setting. The cipher setting is used for configuring the data processing core. The secret key is used for encryption and/or decryption of the data being transferred. All keys are not permanently saved.

    摘要翻译： 用于提供安全的IO设备和存储控制器握手协议的协议; IO设备控制密码设置，以及安全的数据存储和内存访问。 通过加密和/或解密请求数据传输的IO设备从处理器请求会话密钥。 处理器为会话生成一个新的公私密钥对。 公钥被发送到请求的IO设备; 私钥由处理器暂时保存用于会话。 请求的IO设备生成秘密密钥及其期望的密码设置; 此外，使用公钥加密秘密密钥和密码设置，并向处理器发送秘密密钥和密码设置。 处理器使用私钥来解密密钥和密码设置。 密码设置用于配置数据处理核心。 秘密密钥用于对正在传送的数据进行加密和/或解密。 所有键都不会永久保存。

    Hardware assisted non-volatile memory-to-input/output direct memory access (DMA) transfer
    10.
    发明授权
    Hardware assisted non-volatile memory-to-input/output direct memory access (DMA) transfer 失效
    硬件辅助非易失性存储器到输入/输出直接存储器访问（DMA）传输

    公开(公告)号：US07620748B1

    公开(公告)日：2009-11-17

    申请号：US11399736

    申请日：2006-04-06

    申请人： Ricardo Bruce ,  Rey Bruce ,  Federico Zalzos Sambilay, Jr. ,  Bernard Sherwin Leung Chiw

    发明人： Ricardo Bruce ,  Rey Bruce ,  Federico Zalzos Sambilay, Jr. ,  Bernard Sherwin Leung Chiw

    IPC分类号： G06F13/28 ,  G06F13/36

    CPC分类号： G06F13/28

    摘要： In conventional storage device system, data transfer from memory to IO bus has to go through an intermediate volatile memory (cache). Data transfer therefore is completed in two steps—data is transferred from memory to cache and then from cache to the IO bus. Memory-to-cache transfer is handled by one DMA engine and another DMA engine for cache-to-IO transfer. To start the transfer, processor prepares the DMA transfer from memory to cache. Upon completion of the memory-to-cache transfer, the processor is interrupted to prepare the transfer from cache to IO. In between transfers, the processor has to intervene to setup the next transfer utilizing the precious processor cycles. The present invention improves on the above process using two novel schemes; 1) The use of dependency table to facilitate the transfer from memory-to-IO with less intervention from the processor and 2) the use of Bus Snooping scheme to bypass the transfer to cache making the transfer directly from memory to IO bus. This makes the transfer from memory to IO completed in single transfer.

    摘要翻译： 在传统的存储设备系统中，从存储器到IO总线的数据传输必须经过中间的易失性存储器（cache）。 因此，数据传输在两个步骤中完成 - 数据从存储器传输到缓存，然后从缓存传输到IO总线。 内存到高速缓存传输由一个DMA引擎和另一个DMA引擎来处理，用于缓存到IO传输。 为了开始传输，处理器准备从存储器到缓存的DMA传输。 在内存到高速缓存传输完成后，处理器被中断以准备从缓存到IO的传输。 在传输之间，处理器必须介入以利用宝贵的处理器周期设置下一个传输。 本发明使用两种新颖的方案改进了上述过程; 1）使用依赖关系表，以便从处理器的干预更少，从内存到IO的传输，以及2）使用总线侦听方案绕过传输缓存，从而将传输直接从内存传输到IO总线。 这使得从内存到IO的传输在单次传输中完成。