公开(公告)号：US08044484B2

公开(公告)日：2011-10-25

申请号：US12915150

申请日：2010-10-29

申请人： Noriyuki Miura ,  Tadashi Chiba

发明人： Noriyuki Miura ,  Tadashi Chiba

IPC分类号： H01L29/78

CPC分类号： H01L31/02162 ,  H01L27/144 ,  H01L31/105

摘要： The present invention provides an ultraviolet detecting device which comprises a silicon semiconductor layer having a thickness ranging from greater than or equal to 3 nm to less than or equal to 36 nm, which is formed over an insulating layer, lateral PN-junction type first and second photodiodes formed in the silicon semiconductor layer, an interlayer insulating film formed over the silicon semiconductor layer, a first filter layer made of silicon nitride, which is formed over the interlayer insulating film provided over the first photodiode and causes light lying in a wavelength range of an UV-B wave or higher to pass therethrough, and a second filter layer made of silicon nitride, which is formed over the interlayer insulating film provided over the second photodiode and allows light lying in a wavelength range of an UV-A wave or higher to pass therethrough.

摘要翻译： 本发明提供了一种紫外线检测装置，其包括厚度范围大于或等于3nm至小于或等于36nm的硅半导体层，其形成在绝缘层上，首先是横向PN结型， 形成在硅半导体层中的第二光电二极管，形成在硅半导体层上的层间绝缘膜，由氮化硅制成的第一滤光层，形成在设置在第一光电二极管上的层间绝缘膜之上，并且产生波长范围的光 的UV-B波以上通过，以及由氮化硅构成的第二过滤层，其形成在设置在第二光电二极管上的层间绝缘膜的上方，并允许位于UV-A波的波长范围内的光或 较高通过。

公开(公告)号：US07948300B2

公开(公告)日：2011-05-24

申请号：US12539653

申请日：2009-08-12

申请人： Ji-Yeoul Ryoo

发明人： Ji-Yeoul Ryoo

IPC分类号： G05F3/16 ,  H02M3/16

CPC分类号： H02M3/07 ,  H02M2003/071

摘要： A negative supply voltage generating circuit includes a pulse generating circuit and a charge pump. The pulse generating circuit generates a first pulse signal and a second pulse signal in response to a clock signal. The first and second pulse signals have pulse widths different from each other. The charge pump generates a negative supply voltage by performing a charge pumping operation in response to the first and second pulse signals, and has a time interval between a switch-on time duration for charging a flying capacitor and a switch-on time duration for transmitting charges to an output capacitor.

摘要翻译： 负电源电压生成电路包括脉冲发生电路和电荷泵。 脉冲发生电路响应于时钟信号产生第一脉冲信号和第二脉冲信号。 第一和第二脉冲信号具有彼此不同的脉冲宽度。 电荷泵通过响应于第一和第二脉冲信号执行电荷泵送操作而产生负电源电压，并且具有用于对飞溅电容器充电的接通时间段和用于发送的接通时间间隔之间的时间间隔 充电到输出电容器。

公开(公告)号：US07947563B2

公开(公告)日：2011-05-24

申请号：US11704285

申请日：2007-02-09

申请人： Shigenari Aoki

发明人： Shigenari Aoki

IPC分类号： H01L21/76

CPC分类号： H01L23/544 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/5444 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

摘要： A chip forming position specifying method for applying chip IDs indicative of positions on a wafer where semiconductor chips are formed, and thereby specifying their positions. In the chip forming position specifying method, different marks are formed for every chip in a transfer mask (hereinafter called “mark forming mask”) used to form a wiring layer, in addition to normal functional wirings. The positions of the chips on the wafer are respectively specified according to combinations of the marks of a plurality of the mark forming masks, which have been transferred onto the wafer.

摘要翻译： 一种芯片形成位置指定方法，用于将表示位置的芯片ID应用于形成半导体芯片的晶片上，从而指定其位置。 在芯片形成位置指定方法中，除了正常的功能布线之外，在用于形成布线层的转印掩模（以下称为“标记形成掩模”）中的每个芯片都形成不同的标记。 晶片上的芯片的位置分别根据已经转移到晶片上的多个标记形成掩模的标记的组合来指定。

公开(公告)号：US07945062B2

公开(公告)日：2011-05-17

申请号：US11645598

申请日：2006-12-27

申请人： Wei-Chung Wang ,  Sung-Mao Wu ,  Hsueh-An Yang ,  Kuo-Pin Yang ,  Chian-Chi Lin

发明人： Wei-Chung Wang ,  Sung-Mao Wu ,  Hsueh-An Yang ,  Kuo-Pin Yang ,  Chian-Chi Lin

IPC分类号： H04R25/00 ,  H04R9/08 ,  H04R11/04 ,  H04R17/02 ,  H04R19/04 ,  H04R21/02 ,  H01L23/02 ,  H01L23/28

CPC分类号： B81B7/0064 ,  B81B2201/0257 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/16151 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H04R1/02 ,  H04R1/04 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： The invention relates to a microelectromechanical microphone packaging system. The microelectromechanical microphone packaging system comprises a substrate, a chip, a microelectromechanical microphone, a conductive glue, a non-conductive glue and a cover. The substrate has a first surface. The chip is mounted on the first surface of the substrate. The microelectromechanical microphone is mounted on the first surface of the substrate, and electrically connected to the chip. The chip is enclosed by the non-conductive glue. The non-conductive glue is enclosed by the conductive glue. The cover is mounted on the first surface of the substrate to form a containing space, and has an acoustic aperture. The microelectromechanical microphone packaging system utilizes the conductive glue enclosing the chip and the non-conductive glue to shield interference from outside noise and obtain a shielding effect. In addition, the cover does not need to be made of metal material.

摘要翻译： 本发明涉及一种微机电麦克风包装系统。 微电机麦克风包装系统包括基片，芯片，微电机麦克风，导电胶，非导电胶和盖。 衬底具有第一表面。 芯片安装在基板的第一表面上。 微机电麦克风安装在基板的第一表面上，并与芯片电连接。 芯片由非导电胶水封闭。 导电胶被导电胶包围。 盖安装在基板的第一表面上以形成容纳空间，并具有声孔。 微机电麦克风包装系统利用封装芯片和非导电胶的导电胶来屏蔽外部噪声的干扰并获得屏蔽效果。 此外，盖子不需要由金属材料制成。

公开(公告)号：US07928718B2

公开(公告)日：2011-04-19

申请号：US11664170

申请日：2005-09-30

申请人： Ulrik Darling Larsen

发明人： Ulrik Darling Larsen

IPC分类号： G01N27/00 ,  G06M11/02

CPC分类号： G01N15/1227

摘要： A method of calibration of a particle characterization apparatus, and a particle characterization apparatus, in which particles suspended in a liquid are passed through an orifice one by one for characterization of the particles, for instance by Coulter counting. The calibration does not require utilization of special calibration particles or liquids. A priori knowledge of the shape of a typical size distribution of a blood sample is utilized to adjust the apparatus based on an initial relatively short counting period of the sample in question. The initially determined size distribution is compared to the corresponding known typical size distribution and the apparatus is subsequently adjusted to counteract possible differences. Upon adjustment of the apparatus, the remaining part of the sample is passed through the orifice for determination of the actual particle size distribution of the remaining sample.

摘要翻译： 颗粒表征装置的校准方法和颗粒表征装置，其中悬浮在液体中的颗粒逐个通过孔口，用于表征颗粒，例如通过库尔特计数。 校准不需要使用特殊的校准颗粒或液体。 利用血液样本的典型尺寸分布的形状的先验知识来基于所讨论的样品的初始相对较短的计数周期来调节装置。 将初始确定的尺寸分布与相应的已知典型尺寸分布进行比较，随后调整该装置以抵消可能的差异。 在调节设备时，将剩余部分样品通过孔口，以确定剩余样品的实际粒度分布。

公开(公告)号：US07927951B2

公开(公告)日：2011-04-19

申请号：US12955984

申请日：2010-11-30

申请人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

发明人： Tae-Whan Kim ,  Kae-Dal Kwack ,  Sang-Su Park

IPC分类号： H01L21/336 ,  H01L29/788

CPC分类号： H01L29/7887 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7923

摘要： A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

摘要翻译： 非易失性存储器件包括半导体衬底，第一和第二控制栅极以及第一和第二电荷存储模式。 半导体衬底包括具有源极区，漏极区和位于源极和漏极区之间的沟道区的突出的有源管脚。 第一控制栅极位于沟道区的第一侧壁上，第二控制栅位于沟道区的第二侧壁上。 第二控制栅极与第一控制栅极分离。 第一电荷存储图案位于第一侧壁和第一控制栅极之间，第二电荷存储图案位于第二侧壁和第二控制栅极之间。

公开(公告)号：US07916542B2

公开(公告)日：2011-03-29

申请号：US12236771

申请日：2008-09-24

申请人： Ki-Tae Park ,  Hyun-Kyoung Kim

发明人： Ki-Tae Park ,  Hyun-Kyoung Kim

IPC分类号： G11C11/34

CPC分类号： G11C16/3418

摘要： A nonvolatile memory device includes a memory cell array having multiple memory cells arranged at intersections of word lines and bit lines, a first page region configured with at least two adjacent memory cells coupled to a word line, and a second page region configured with at least two adjacent memory cells coupled to the word line. The nonvolatile memory devices also includes a first common source line connecting with the memory cells of the first page region, and a second common source line connecting with the memory cells of the second page region. The first and second common source lines are controlled independently.

摘要翻译： 非易失性存储器件包括存储单元阵列，其具有布置在字线和位线的交点处的多个存储器单元，配置有耦合到字线的至少两个相邻存储器单元的第一页区域和至少配置有第二页区域 耦合到字线的两个相邻的存储单元。 非易失性存储器件还包括与第一页区域的存储单元连接的第一公共源极线和与第二页区域的存储器单元连接的第二公共源极线。 第一和第二公共源极线独立控制。

公开(公告)号：US07911056B2

公开(公告)日：2011-03-22

申请号：US11651540

申请日：2007-01-10

申请人： Pai-Chou Liu ,  Yu-Hsin Lee

发明人： Pai-Chou Liu ,  Yu-Hsin Lee

IPC分类号： H01L23/48

CPC分类号： H05K3/3452 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05552 ,  H01L2224/05555 ,  H01L2224/05571 ,  H05K2201/0989 ,  H05K2201/10734 ,  H01L2924/00014 ,  H01L2924/00012

摘要： A substrate structure having non-solder mask design (N-SMD) ball pads. The substrate structure includes a substrate and a solder mask. The substrate has a first surface, a trace layer and at least one ball pad. The ball pad and the trace layer are disposed on the first surface. The trace layer has a plurality of traces, and at least one trace electrically connects to the ball pad. The solder mask has at least one opening corresponding to the ball pad. The size of the opening is larger than that of the ball pad. The solder mask covers the trace connecting to the ball pad. The problem of non-alignment of the solder ball can thus be solved, and the hole in the solder ball can be prevented when the substrate structure is welded with a PCB so that the reliability of solder ball welding can be improved.

摘要翻译： 具有非焊锡掩模设计（N-SMD）球垫的衬底结构。 衬底结构包括衬底和焊接掩模。 基板具有第一表面，迹线层和至少一个球垫。 球垫和轨迹层设置在第一表面上。 迹线层具有多个迹线，并且至少一个轨迹电连接到球垫。 焊接掩模具有至少一个对应于球垫的开口。 开口的尺寸大于球垫的尺寸。 焊接掩模覆盖连接到球垫的迹线。 因此可以解决焊球不对准的问题，并且当用PCB焊接衬底结构时可以防止焊球中的孔，从而可以提高焊球焊接的可靠性。

公开(公告)号：US07875909B2

公开(公告)日：2011-01-25

申请号：US11600829

申请日：2006-11-17

申请人： Hirofumi Uchida

发明人： Hirofumi Uchida

IPC分类号： H01L27/10

CPC分类号： H01L27/0207 ,  H01L27/11807 ,  H03K17/693 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778 ,  H03K19/17796

摘要： A gate array of a semiconductor substrate on which plural unit cells are arranged in parallel, the unit cells having the same pattern that includes a source potential region VDD, a PMOS, an NMOS and a ground potential region GND. Metal wiring lines being formed, with an insulating layer between, on the unit cells, with contacts that make electrical connection between the metal wiring lines and the unit cell transistors. The gate wiring of a transistor in a non-used unit cell is used in place of a metal wiring line. By doing so, the area of metal wiring lines in a gate array is reduced and the array wiring efficiency is increased.

摘要翻译： 并联布置多个单位电池的半导体基板的栅极阵列，具有包括源极电位区域VDD，PMOS，NMOS以及接地电位区域GND的相同图案的单元电池。 在单元电池之间形成有绝缘层的金属布线与在金属布线和单元晶体管之间形成电连接的触点。 使用未使用的单元电池中的晶体管的栅极布线代替金属布线。 通过这样做，栅极阵列中的金属布线的面积减小，阵列布线效率提高。

公开(公告)号：US07868420B2

公开(公告)日：2011-01-11

申请号：US12014331

申请日：2008-01-15

申请人： Daisuke Inomata

发明人： Daisuke Inomata

IPC分类号： H01L29/92

CPC分类号： H01L21/7687 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate and a capacitor which is disposed on a principal surface of the semiconductor substrate. The capacitor includes a lower electrode film disposed on the principal surface of the semiconductor substrate, a dielectric film disposed on the lower electrode and an upper electrode film disposed on the dielectric film. The semiconductor device further includes an interconnection film which includes a portion disposed on the upper electrode film so as to be electrically coupled to the upper electrode film. Directions of residual stresses of the upper electrode film coincide with directions of residual stresses of the portion of the interconnection film. Each of the upper electrode film and the interconnection film may include at least one of platinum and iridium. Also, there is provided a method of manufacturing the semiconductor device.

摘要翻译： 半导体器件包括半导体衬底和设置在半导体衬底的主表面上的电容器。 电容器包括设置在半导体衬底的主表面上的下电极膜，设置在下电极上的电介质膜和设置在电介质膜上的上电极膜。 半导体器件还包括互连膜，其包括设置在上电极膜上以与上电极膜电耦合的部分。 上电极膜的残余应力的方向与互连膜的部分的残余应力的方向一致。 上电极膜和互连膜中的每一个可以包括铂和铱中的至少一种。 另外，提供一种制造半导体器件的方法。