公开(公告)号：US12227326B2

公开(公告)日：2025-02-18

申请号：US17970082

申请日：2022-10-20

Applicant: Irwin Research and Development, Inc.

Inventor： Dale L Vantrease

IPC: B65B51/04 ,  B65B7/02

Abstract: A closure strip guide is provided having a front plate, a back plate and a plate keeper. The back plate is carried proximate and spaced from the front plate to provide a gap thickness configured to guide a strip of clips. The plate keeper is configured to retain together the front plate and the back plate to retain the gap thickness to slidably receive and guide the strip of clips. The plate keeper also expands the gap thickness between the front plate and the back plate responsive to a stack-up jam to accommodate multiple layers of clips in the event the strip of clips dislodges and/or jams. A bag closing apparatus and a method are also provided.

公开(公告)号：US12225721B2

公开(公告)日：2025-02-11

申请号：US17841925

申请日：2022-06-16

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H10B41/27 ,  H10B41/10 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Spaced insulator-material bodies are formed in and longitudinally-along opposing sides of individual of the memory-block regions in a lowest of the first tiers. After forming the spaced insulator-material bodies, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US12213311B2

公开(公告)日：2025-01-28

申请号：US17670685

申请日：2022-02-14

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Alyssa N. Scarbrough

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions, Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally therealong in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.

公开(公告)号：US12202441B2

公开(公告)日：2025-01-21

申请号：US18107394

申请日：2023-02-08

Applicant: Van Straten Enterprises, Inc.

Inventor： George Van Straten

IPC: B60R9/045 ,  B60R9/055 ,  B60R9/06 ,  B60R9/10 ,  B60R16/033 ,  H02S10/40 ,  H02S30/20 ,  H02S40/12 ,  H02S40/38

Abstract: A vehicle bed deployable solar power unit and cargo hauler assembly includes an articulating platform frame, a solar panel and a cargo carrier. The solar panel is carried by the articulating frame moveable between a stowed position and a deployed position. The cargo carrier is supported by the articulating platform frame movable relative to the solar panel to prevent operational interference between the solar panel in articulated positions and the cargo carrier. A method is also provided.

公开(公告)号：US12192940B2

公开(公告)日：2025-01-07

申请号：US17703879

申请日：2022-03-24

Applicant: Sierra Wireless, Inc.

Inventor： Gautham Prasad ,  Nadhem Rojbi ,  Gustav Gerald Vos ,  Lutz Hans-Joachim Lampe

IPC: H04W56/00 ,  H04B17/318

Abstract: There are provided methods for predicting timing advance (TA) with respect to a base station. According to some embodiments, the method includes determining, by a user equipment (UE), a set of TAs, each TA corresponding to a particular distance from the base station and measuring, by the UE, a set of instances of a power metric, each instance of the power metric associated with a respective distance from the base station. The method further includes determining, by the UE, a set of differences between each of the instances of the power metric and determining, by the UE, a new TA at least in part using the set of TAs and the set of differences.

公开(公告)号：US12188036B2

公开(公告)日：2025-01-07

申请号：US16755453

申请日：2018-10-11

Applicant: CELLTRION INC.

Inventor： Man Su Kim ,  Min Soo Kim ,  Jong Moon Cho ,  Shin Jae Chang

IPC: C12N15/85 ,  C07K16/00 ,  C12N15/11 ,  C12N15/113

Abstract: The present invention relates to an expression cassette for a target protein, comprising a promoter, a polynucleotide coding for the target protein, an intron sequence, and a poly A sequence, an expression vector, and a transformant. The expression cassette for a target protein according to the present invention can simultaneously perform the expression of the intron sequence and the target protein through one transduction and exhibits the effect of inducing the high expression and high functionality of the target protein by regulating the expression of an endogenous gene.

公开(公告)号：US12182214B1

公开(公告)日：2024-12-31

申请号：US18204668

申请日：2023-06-01

Applicant: GROWPATH, LLC

Inventor： Eric Jason Sanchez ,  Jan Schroeder ,  Richard Christopher Low

IPC: G06F16/9535 ,  G06F16/242 ,  G06F40/169 ,  G06Q10/107 ,  G06Q30/01

Abstract: A method includes providing a server having a system email address for receiving emails and including a processor and a memory coupled to the processor and defining a database organized to store data for a plurality of customer matters, respective matters having matter numbers, and, for each matter, the database including a notes location associated with the matter; providing a graphical user interface using which a user can review information relating to matters, including notes; determining, in response to receiving an email having a subject line and body, if the email contains a matter number matching a database matter number and, if not, rejecting the email; and if the email is not rejected, routing at least a portion of the non-rejected email to the notes location of the matter. Other systems and methods are provided.

公开(公告)号：US12176034B2

公开(公告)日：2024-12-24

申请号：US17583472

申请日：2022-01-25

Applicant: Micron Technology, Inc.

Inventor： Alyssa N. Scarbrough ,  M. Jared Barclay ,  John D. Hopkins

IPC: H01L29/76 ,  G11C16/04 ,  H01L23/522 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through a lowest of the conductive tiers. Insulative rings are in the lowest conductive tier in the TAV region. Individual of the insulative rings encircle individual of the TAVs. The insulative rings extend through the lowest conductive tier and into the conductor tier. Outer rings are in the lowest conductive tier that individually encircle one of the individual insulative rings that encircle the individual TAVs. Other embodiments, including method, are disclosed.

公开(公告)号：US12167586B2

公开(公告)日：2024-12-10

申请号：US17460156

申请日：2021-08-27

Applicant: Micron Technology, Inc.

Inventor： Giorgio Servalli ,  Marcello Mariani

IPC: H10B12/00 ,  G11C11/22 ,  H10B53/10 ,  H10B53/30

Abstract: Some embodiments include an assembly having first and second pillars. Each of the pillars has an inner edge and an outer edge. A first gate is proximate a channel region of the first pillar. A second gate is proximate a channel region of the second pillar. A shield line is between the first and second pillars. First and second bottom electrodes are over the first and second pillars, respectively; and are configured as first and second angle plates. An insulative material is over the first and second bottom electrodes. The insulative material may be ferroelectric or non-ferroelectric. A top electrode is over the insulative material. Some embodiments include methods of forming assemblies.

公开(公告)号：US12142680B2

公开(公告)日：2024-11-12

申请号：US17317636

申请日：2021-05-11

Applicant: Micron Technology, Inc.

Inventor： Sanh D. Tang ,  Hong Li ,  Erica L. Poelstra

IPC: H01L29/78 ,  H01L21/02 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/762 ,  H01L21/8234 ,  H01L23/49 ,  H01L23/528 ,  H01L29/06 ,  H01L29/10 ,  H01L29/66 ,  H10B12/00 ,  H10B63/00 ,  H01L21/764

Abstract: Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.