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公开(公告)号：US11508853B2
公开(公告)日：2022-11-22
申请号：US16940789
申请日：2020-07-28
发明人： Chih-Ting Yeh , Sung-Chih Huang , Che-Hao Chuang
IPC分类号： H01L29/861 , H01L29/06 , H01L29/08
摘要： A vertical bipolar transistor device includes a heavily-doped semiconductor substrate, a first semiconductor epitaxial layer, at least one doped well, an isolation structure, and an external conductor. The heavily-doped semiconductor substrate and the doped well have a first conductivity type, and the first semiconductor epitaxial layer has a second conductivity type. The first semiconductor epitaxial layer is formed on the heavily-doped semiconductor substrate. The doped well is formed in the first semiconductor epitaxial layer. The isolation structure, formed in the heavily-doped semiconductor substrate and the first semiconductor epitaxial layer, surrounds the first semiconductor epitaxial layer and the at least one doped well. The external conductor is arranged outside the first semiconductor epitaxial layer and the doped well and electrically connected to the first semiconductor epitaxial layer and the doped well.
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公开(公告)号：US20200058636A1
公开(公告)日：2020-02-20
申请号：US16105310
申请日：2018-08-20
发明人： KUN-HSIEN LIN , ZI-PING CHEN , CHE-HAO CHUANG
IPC分类号： H01L27/02 , H01L27/06 , H01L29/735 , H01L29/08 , H01L27/082 , H01L29/06
摘要： A transient voltage suppression device includes a lightly-doped semiconductor structure, a first doped well, a first heavily-doped area, a first buried area, and a second heavily-doped area. The lightly-doped semiconductor structure has a first conductivity type. The first doped well has a second conductivity type and is formed in the lightly-doped semiconductor structure. The first heavily-doped area has the second conductivity type and is formed in the first doped well. The first buried area has the first conductivity type and is formed in the lightly-doped semiconductor structure and under the first doped well, and the first buried area is adjacent to the first doped well. The second heavily-doped area has the second conductivity type and is formed in the lightly-doped semiconductor structure.
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公开(公告)号：US10468513B1
公开(公告)日：2019-11-05
申请号：US16117147
申请日：2018-08-30
发明人： Chih-Wei Chen , Kun-Hsien Lin
IPC分类号： H01L29/747 , H01L29/06 , H01L27/02
摘要： A bidirectional silicon-controlled rectifier includes a lightly-doped semiconductor structure, a first lightly-doped region, a second lightly-doped region, a first doped well, a second doped well, a first heavily-doped area, a second heavily-doped area, a third heavily-doped area, a fourth heavily-doped area. The lightly-doped semiconductor structure, the first heavily-doped area, and the third heavily-doped area have a first conductivity type. The first lightly-doped region, the second lightly-doped region, the first doped well, the second doped well, the fourth heavily-doped area, and the second heavily-doped area have a second conductivity type. A first part of the first lightly-doped region is arranged under the first doped well. A second part of the second lightly-doped region is arranged under the second doped well.
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公开(公告)号：US10388647B1
公开(公告)日：2019-08-20
申请号：US16105318
申请日：2018-08-20
发明人： Kun-Hsien Lin , Zi-Ping Chen , Che-Hao Chuang
IPC分类号： H01L29/74 , H01L31/111 , H01L27/02 , H01L23/528 , H01L27/06 , H01L29/861 , H01L29/735
摘要： An improved transient voltage suppression device includes a semiconductor substrate, a transient voltage suppressor, at least one first diode, at least one conductive pad, and at least one second diode. The transient voltage suppressor has an N-type heavily-doped clamping area. The first anode of the first diode is electrically connected to the N-type heavily-doped clamping area. The conductive pad is electrically connected to the first cathode of the first diode. The second anode of the second diode is electrically connected to the conductive pad and the second cathode of the second diode is electrically connected to the transient voltage suppressor. The first anode is closer to the N-type heavily-doped clamping area rather than the conductive pad. The conductive pad is closer to the N-type heavily-doped clamping area rather than the second anode.
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公开(公告)号：US09748219B1
公开(公告)日：2017-08-29
申请号：US15241365
申请日：2016-08-19
IPC分类号： H01L27/02 , H01L23/528
CPC分类号： H01L27/0262 , H01L23/528 , H01L29/0657 , H01L29/0692 , H01L29/87
摘要： A self-balanced silicon-controlled rectification device includes a substrate, an N-type doped well, a P-type doped well, at least one heavily doped clamping fin, at least one first P-type heavily doped fin, and at least one first N-type heavily doped fin. The N-type doped well and the P-type doped well are arranged in the substrate. The heavily doped clamping fin is arranged in the N-type doped well and the P-type well and protruded up from a surface of the substrate. The first P-type heavily doped fin and the first N-type heavily doped fin are respectively arranged in the N-type doped well and the P-type doped well, and protruded up from the surface of the substrate. The abovementioned elements forms silicon-controlled rectifiers (SCRs) are forward biased to generate uniform electrostatic discharge (ESD) currents through the SCRs.
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公开(公告)号：US09224702B2
公开(公告)日：2015-12-29
申请号：US14104251
申请日：2013-12-12
发明人： Ming-Dou Ker , Che-Hao Chuang
CPC分类号： H01L23/60 , H01L23/66 , H01L24/16 , H01L24/17 , H01L25/0655 , H01L25/0657 , H01L2224/16 , H01L2224/16146 , H01L2224/16227
摘要： A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.
摘要翻译： 公开了一种三维（3D）集成电路（IC）封装。 3D IC封装具有具有表面的封装衬底。 具有或不抑制瞬态电压的至少一个集成电路（IC）芯片和至少一个瞬态电压抑制器（TVS）芯片布置在基板的表面上并彼此电连接。 IC芯片独立于TVS芯片。 彼此堆叠的IC芯片和TVS芯片布置在封装基板上。 或者，IC芯片和TVS芯片一起排列在形成在封装基板上的插入件上。
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公开(公告)号：US20140106064A1
公开(公告)日：2014-04-17
申请号：US14109297
申请日：2013-12-17
IPC分类号： H01J9/02
CPC分类号： H01J9/02 , H01J17/066
摘要： A method for fabricating a semiconductor-based planar micro-tube discharger structure is provided, including the steps of forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap, forming an insulating layer over the patterned electrodes and the separating block., and filling the insulating layer into the gap. At least two discharge paths are formed. The method can fabricate a plurality of discharge paths in a semiconductor structure, the structure having very high reliability and reusability.
摘要翻译： 提供一种制造基于半导体的平面微管放电器结构的方法，包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块，在图案上形成绝缘层 电极和分离块，并将绝缘层填充到间隙中。 形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径，该结构具有非常高的可靠性和可再利用性。
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公开(公告)号：US20230010423A1
公开(公告)日：2023-01-12
申请号：US17368269
申请日：2021-07-06
发明人： Tun-Chih YANG , Zi-Ping CHEN , Kun-Hsien LIN
IPC分类号： H01L27/02
摘要： A multi-channel transient voltage suppression device includes a semiconductor substrate, a semiconductor layer, at least two bidirectional transient voltage suppression structures, and at least one isolation trench. The semiconductor substrate, having a first conductivity type, is coupled to a grounding terminal. The semiconductor layer, having a second conductivity type opposite to the first conductivity type, is formed on the semiconductor substrate. The bidirectional transient voltage suppression structures are formed in the semiconductor layer. Each bidirectional transient voltage suppression structure is coupled to an input/output (I/O) pin and the grounding terminal. The isolation trench is formed in the semiconductor substrate and the semiconductor layer and formed between the bidirectional transient voltage suppression structures. The isolation trench has a height larger than the height of the semiconductor layer and surrounds the bidirectional transient voltage suppression structures.
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公开(公告)号：US11515900B1
公开(公告)日：2022-11-29
申请号：US17390038
申请日：2021-07-30
发明人： Guan-Shun Li
摘要： A transmitter circuit applicable to a digital isolator is provided, adapted to receive a data input signal and coupled to an isolation barrier, developing a receiver input signal to a receiver circuit for generating a data output signal. The transmitter circuit generates a transmitter output signal in response to a rising edge and falling edge of the data input signal, and includes a rising and falling converter for outputting a converted data input signal according to the rising edge and falling edge of the data input signal, a delay and logic unit for receiving the converted data input signal and generating a carrier signal, and an AND gate receiving the converted data input signal and the carrier signal, and outputting the transmitter output signal. Since a number of pulses of the carrier signal is limited and definite, the present invention achieves to reduce power consumption and electromagnetic interferences effectively.
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公开(公告)号：US20220200272A1
公开(公告)日：2022-06-23
申请号：US17132389
申请日：2020-12-23
发明人： Chih-Ting YEH , Sung-Chih HUANG , Che-Hao CHUANG
摘要： A transient voltage suppression device includes at least one diode string, a power clamp device, at least one first bypass diode, and at least two second bypass diodes. The diode string is coupled between a power terminal and a common bus and coupled to an input output (I/O) port. The power clamp device is coupled between the power terminal and the common bus. The first bypass diode is coupled between the common bus and a ground terminal The second bypass diodes are coupled in series, coupled between the common bus and the ground terminal, and coupled to the first bypass diode in reverse parallel. Alternatively, the first bypass diode and the second bypass diodes are replaced with at least one bi-directional electrostatic discharge (ESD) device.
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