公开(公告)号：US20250164246A1

公开(公告)日：2025-05-22

申请号：US18944411

申请日：2024-11-12

Applicant: Analog Devices, Inc.

Inventor： Tyler Dunn ,  Gaurav Vohra ,  William Clark ,  Xin Zhang ,  Carey Merritt

IPC: G01C19/5712

Abstract: Gyroscopes with electrodes for tuning cross-axis sensitivity are disclosed. In certain embodiments, a MEMS gyroscope includes a resonator mass that moves in a first direction (for instance, x-direction), a sensing structure that detects a Coriolis effect in a second direction (for instance, y-direction), and a plurality of electrodes that control a cross-axis stiffness of the MEMS gyroscope by controlling motion of the resonator mass in a third direction (for instance, z-direction). For example, the electrodes can be used to reduce or eliminate cross-axis sensitivity arising from cross-axis stiffnesses, such as kxz (resonator-to-orthogonal) and/or kyz (Coriolis-to-orthogonal).

公开(公告)号：US20250158626A1

公开(公告)日：2025-05-15

申请号：US18945092

申请日：2024-11-12

Applicant: Analog Devices, Inc.

Inventor： Yaohua YANG ,  Benjamin John McCarroll ,  Min Park

IPC: H03M1/08 ,  A61B5/00

Abstract: Aspects of the present disclosure provide methods and apparatuses for operating an analog-to-digital converter. A method in accordance with an aspect of the present disclosure may comprise initializing a digital-to-analog converter (DAC) value of a DAC, determining whether an analog-to-digital converter (ADC) operates within a predetermined range based on an input to the DAC, initiating a conversion at a first ADC resolution when the ADC is operating within the predetermined range, and incrementally changing the DAC value when the ADC is not operating within the predetermined range.

公开(公告)号：US20250158578A1

公开(公告)日：2025-05-15

申请号：US18924349

申请日：2024-10-23

Applicant: Analog Devices, Inc.

Inventor： Arthur J. Kalb ,  Yoshinori Kusuda

IPC: H03F1/52 ,  H02H3/20 ,  H02M1/32

Abstract: Apparatus and methods for amplifier input-overvoltage protection with low leakage current are provided herein. In certain embodiments, amplifier input circuitry for an amplifier includes a pair of input terminals, a pair of input transistors each having a control input (for instance, a transistor gate), a pair of protection transistors each connected between one of the input terminals and the control input of a corresponding one of the input transistors, and a bidirectional clamp connected between the control inputs of the input transistors. Implementing the amplifier input circuitry in this manner provides a number of advantages including, but not limited to, robust protection against input overvoltage and low input-leakage current.

公开(公告)号：US20250138060A1

公开(公告)日：2025-05-01

申请号：US18498731

申请日：2023-10-31

Applicant: Analog Devices, Inc.

Inventor： Eric A. Sagen ,  Gregory J. Manlove

IPC: G01R19/25

Abstract: Described are techniques to provide a gain trim term in the numerator for a current sensor control loop. In this manner, a linear gain trim relationship is created with respect to the trim code. This linear relationship reduces the dynamic range needed for the DAC, which allows the use of lower resolution DACs to smoothly adjust the gain while maintaining stability and accuracy.

公开(公告)号：US12287437B2

公开(公告)日：2025-04-29

申请号：US18065045

申请日：2022-12-13

Applicant: Analog Devices, Inc.

Inventor： Patrick S. Riehl ,  Sunrita Poddar

IPC: G01T1/17 ,  A61B6/03 ,  A61B6/42

Abstract: One embodiment is a method for counting charge events detected by a pixel in a photon-counting computed tomography (PCCT) scanning system comprising a plurality of discriminators, wherein each discriminator is associated with a respective one of a plurality of threshold voltage levels. The method includes detecting a signal output from one of the discriminators; incrementing a quantitative count corresponding to the threshold voltage level associated with the one of the discriminators if the detected discriminator output signal meets a first condition; and incrementing a qualitative count if the detected discriminator output signal meets at least one second condition.

公开(公告)号：US20250118715A1

公开(公告)日：2025-04-10

申请号：US18730912

申请日：2023-01-24

Applicant: Analog Devices, Inc.

Inventor： Xin Zhang ,  Jianglong Zhang ,  Li Chen ,  John C. Cowles ,  Michael Judy ,  Shafi Saiyed

IPC: H01L25/16 ,  B81B7/00 ,  H01L23/538

Abstract: Compact packages including microelectromechanical system (MEMS) devices and multiple application specific integrated circuits (ASICs) are described. These packages are sufficiently small to be applicable to contexts in which space requirements are particularly strict, such as in consumer electronics. These packages involve vertical die stacks. A first ASIC may be positioned on one side of the die stack and another ASIC may be positioned on the other side of the die stack. A die including a MEMS device (e.g., an accelerometer, gyroscope, switch, resonator, optical device) is positioned between the ASICs. Optionally, an interposer serving as cap substrate for the MEMS device is also positioned between the ASICs. In one example, a package of the types described herein has an extension of 2 mm×2 mm in the planar axes and less than 500-800 μm in height.

公开(公告)号：US12271216B2

公开(公告)日：2025-04-08

申请号：US18040025

申请日：2021-11-30

Applicant: Analog Devices, Inc.

Inventor： Petrus M. Stroet

IPC: G05F1/59 ,  G05F1/46 ,  H01L31/02

Abstract: Apparatus and methods for logarithmic current to voltage conversion are disclosed herein. In certain embodiments, a logarithmic current to voltage converter includes an input terminal that receives an input current, an output terminal that provides a logarithmic output voltage, a first field-effect transistor (FET) having a gate connected to the input terminal, a first bipolar transistor having a collector connected to the input terminal and an emitter connected to the output terminal, and a stacked transistor connected to the output terminal and to the first FET to form a feedback loop. For example, the stacked transistor can correspond to a second bipolar transistor having a collector connected to the output terminal and a base connected to the source of the first FET, or to a second FET having a drain connected to the output terminal and a gate connected to the source of the first FET.

公开(公告)号：US12261608B2

公开(公告)日：2025-03-25

申请号：US18247691

申请日：2021-12-07

Applicant: Analog Devices, Inc.

Inventor： Hyman Shanan ,  John Kenney

IPC: H03D3/24 ,  H03L1/02 ,  H03L7/099 ,  H03L7/189 ,  H04B1/16

Abstract: Apparatus and methods for control and calibration of external oscillators are provided herein. In certain embodiments, an electronic oscillator system includes a semiconductor die and a controllable oscillator that is external to the semiconductor die. The oscillation frequency of the controllable oscillator is tuned by a first varactor and a second varactor. The semiconductor die includes a phase-locked loop (PLL) that provides fine tuning to the controllable oscillator by controlling the first varactor, and a calibration circuit that provides coarse tuning to the controllable oscillator by controlling the second varactor.

公开(公告)号：US20250098200A1

公开(公告)日：2025-03-20

申请号：US18940279

申请日：2024-11-07

Applicant: Analog Devices, Inc.

Inventor： James G. Fiorenza ,  Puneet Srivastava ,  Daniel Piedra

IPC: H01L29/778 ,  H01L21/265 ,  H01L21/266 ,  H01L27/088 ,  H01L29/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: An enhancement mode compound semiconductor field-effect transistor (FET) includes a source, a drain, and a gate located therebetween. The transistor further includes a first gallium nitride-based hetero-interface located under the gate and a buried region, located under the first hetero-interface, the buried p-type region configured to determine an enhancement mode FET turn-on threshold voltage to permit current flow between the source and the drain.

公开(公告)号：US20250088340A1

公开(公告)日：2025-03-13

申请号：US18464512

申请日：2023-09-11

Applicant: Analog Devices, Inc.

Inventor： Martin KESSLER ,  Lewis F. LAHR ,  William HOOPER ,  Matthew PUZEY

IPC: H04L5/14 ,  H04L7/00

Abstract: A communication system includes a plurality of nodes connected in a daisy-chain via respective bus links, wherein the plurality of nodes are configured for full duplex, synchronized communication via a carrier-based modulation scheme over the bus links. A node is configured to: transmit a downstream synchronization control header (DnSCH) to a downstream node; receive an upstream synchronization response header (UpSRH) from the downstream node; measure a delay between the DnSCH and the UpSRH; send delay information to the downstream node in a DnSCH; receive a time adjusted UpSRH; and communicate with the downstream node and any upstream node over frames based on the delay information. The frames may include a header; a flexible payload defined by a stream mapping that assigns a byte location within the flexible payload to a stream; and a footer.