Adapter card for connection to a data bus in a data processing unit and method for operating a DDR memory module
    1.
    发明授权
    Adapter card for connection to a data bus in a data processing unit and method for operating a DDR memory module 失效
    用于连接到数据处理单元中的数据总线的适配器卡和用于操作DDR存储器模块的方法

    公开(公告)号:US07624315B2

    公开(公告)日:2009-11-24

    申请号:US10884110

    申请日:2004-07-02

    IPC分类号: G11C29/00 G11C7/00

    CPC分类号: G11C29/48 G11C2029/0401

    摘要: One embodiment of the invention provides an adapter card for connection to a data bus in a data processing unit. The adapter includes a DDR interface for connection of a DDR memory module, a memory unit for storing test mode data, a switching device, which, in a first switching state, connects the data bus to the DDR interface and, in a second switching state, decouples the DDR interface from the data bus and connects the memory unit to the DDR interface such that test mode data may be transmitted to a connected DDR memory module to call up a test mode in the DDR memory module. The adapter also includes a control circuit with a trigger input to control the switching device between the switching states depending on a trigger signal.

    摘要翻译: 本发明的一个实施例提供一种用于连接到数据处理单元中的数据总线的适配器卡。 适配器包括用于连接DDR存储器模块的DDR接口,用于存储测试模式数据的存储器单元,开关器件,其在第一开关状态下将数据总线连接到DDR接口,并且在第二切换状态 ,将DDR接口与数据总线分离,并将存储器单元连接到DDR接口,使测试模式数据可以传输到连接的DDR存储器模块,以调用DDR存储器模块中的测试模式。 适配器还包括具有触发输入的控制电路,以根据触发信号在切换状态之间控制开关装置。

    Method and apparatus for checking output signals of an integrated circuit
    3.
    发明授权
    Method and apparatus for checking output signals of an integrated circuit 失效
    用于检查集成电路的输出信号的方法和装置

    公开(公告)号:US07380182B2

    公开(公告)日:2008-05-27

    申请号:US10933645

    申请日:2004-09-03

    IPC分类号: G01R31/28

    摘要: Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

    摘要翻译: 提供了用于检查集成电路的输出信号的装置和方法。 一个实施例提供了一种用于根据预定义的规范来检查信号是否由集成电路的写入电路输出的方法。 在这种情况下,系统固有的外部测试装置的高精度用于在模块内检查根据规格输出集成电路的数据信号和数据采样信号。

    Adapter card for connection to a data bus in a data processing unit and method for operating a DDR memory module
    4.
    发明申请
    Adapter card for connection to a data bus in a data processing unit and method for operating a DDR memory module 失效
    用于连接到数据处理单元中的数据总线的适配器卡和用于操作DDR存储器模块的方法

    公开(公告)号:US20050034025A1

    公开(公告)日:2005-02-10

    申请号:US10884110

    申请日:2004-07-02

    IPC分类号: G11C29/00 G11C29/48 H04B1/74

    CPC分类号: G11C29/48 G11C2029/0401

    摘要: One embodiment of the invention provides an adapter card for connection to a data bus in a data processing unit. The adapter includes a DDR interface for connection of a DDR memory module, a memory unit for storing test mode data, a switching device, which, in a first switching state, connects the data bus to the DDR interface and, in a second switching state, decouples the DDR interface from the data bus and connects the memory unit to the DDR interface such that test mode data may be transmitted to a connected DDR memory module to call up a test mode in the DDR memory module. The adapter also includes a control circuit with a trigger input to control the switching device between the switching states depending on a trigger signal.

    摘要翻译: 本发明的一个实施例提供一种用于连接到数据处理单元中的数据总线的适配器卡。 适配器包括用于连接DDR存储器模块的DDR接口,用于存储测试模式数据的存储器单元,开关器件,其在第一开关状态下将数据总线连接到DDR接口,并且在第二切换状态 ,将DDR接口与数据总线分离,并将存储器单元连接到DDR接口,使测试模式数据可以传输到连接的DDR存储器模块,以调用DDR存储器模块中的测试模式。 适配器还包括具有触发输入的控制电路,以根据触发信号在切换状态之间控制开关装置。

    Method and apparatus for testing an SDRAM memory used as the main memory in a personal computer
    5.
    发明授权
    Method and apparatus for testing an SDRAM memory used as the main memory in a personal computer 失效
    用于测试在个人计算机中用作主存储器的SDRAM存储器的方法和装置

    公开(公告)号:US06775795B2

    公开(公告)日:2004-08-10

    申请号:US09789991

    申请日:2001-02-20

    IPC分类号: G11C2900

    CPC分类号: G11C29/56 G11C11/401

    摘要: A method and an apparatus for testing an SDRAM are described. The SDRAM is used as a main memory in the PC, and an additional circuit configuration is accommodated on a plug-in board and has an additional memory in the form of an SRAM and logic circuits. The method according to the invention allows the SDRAM to be tested in a module bank in the running PC to be set deliberately to a test mode. In this case the code for test mode activation is modified by a high-level language program (PASCAL) in accordance with the user requirements, is copied to the additional memory on the plug-in board, and is then called by the high-level language program using MS DOS. After activation of the selected test mode by a code programmed in Assembler, a defined jump is made back to the calling program once again. This allows the use of the test mode provided in the SDRAM in standard PCs and using standard operating systems. This greatly increases the test options for SDRAMs on standard PCs.

    摘要翻译: 描述了用于测试SDRAM的方法和装置。 SDRAM用作PC中的主存储器,附加电路配置被容纳在插入板上,并且具有SRAM和逻辑电路形式的附加存储器。 根据本发明的方法允许在运行的PC中的模块组中测试SDRAM被故意地设置为测试模式。 在这种情况下,根据用户需求,通过高级语言程序(PASCAL)修改测试模式激活的代码,被复制到插件板上的附加存储器中,然后由高级别 语言程序使用MS DOS。 通过在汇编程序中编程的代码激活所选的测试模式后,定义的跳转将再次返回到调用程序。 这允许在标准PC中使用SDRAM中提供的测试模式并使用标准操作系统。 这大大增加了标准PC上SDRAM的测试选项。

    Circuit and Method for Limiting a Current Flow in Case of a Shortage of a Support Capacitor
    7.
    发明申请
    Circuit and Method for Limiting a Current Flow in Case of a Shortage of a Support Capacitor 审中-公开
    在支持电容器不足的情况下限制电流的电路和方法

    公开(公告)号:US20090295342A1

    公开(公告)日:2009-12-03

    申请号:US12127458

    申请日:2008-05-27

    IPC分类号: G05F3/16

    CPC分类号: G11C5/063

    摘要: A circuit includes a voltage supply net, a first capacitor connected between the voltage supply net and a reference potential via a first transistor, and a second capacitor connected between the voltage supply net and the reference potential via a second transistor, such that the first and the second capacitor form at least a part of a support capacitance for the voltage supply net. The circuit is configured to provide control signals to control terminals of the first and second transistor such that the first transistor allows for a limited current flow in case of a shortage of the first capacitor and such that the second transistor allows for a limited current flow in case of a shortage of the second capacitor.

    摘要翻译: 电路包括电压供应网,经由第一晶体管连接在电压源和参考电位之间的第一电容器,以及经由第二晶体管连接在电压源和参考电位之间的第二电容器,使得第一和 第二电容器形成用于电压网的支撑电容的至少一部分。 电路被配置为向第一和第二晶体管的控制端提供控制信号,使得第一晶体管在第一电容器不足的情况下允许有限的电流流动,并且使得第二晶体管允许有限的电流在 第二电容器短缺的情况。

    Method and apparatus for checking output signals of an integrated circuit
    8.
    发明申请
    Method and apparatus for checking output signals of an integrated circuit 失效
    用于检查集成电路的输出信号的方法和装置

    公开(公告)号:US20050114734A1

    公开(公告)日:2005-05-26

    申请号:US10933645

    申请日:2004-09-03

    IPC分类号: G11C29/50 G06F11/00

    摘要: Apparatus and method for checking output signals of an integrated circuit are provided. One embodiment provides a method for checking whether signals are output by a write circuit of an integrated circuit according to a predefined specification. In this context, the high precision of an external test device which is inherent to the system is used to check, within a module, that a data signal and a data sampling signal of the integrated circuit are output according to a specification.

    摘要翻译: 提供了用于检查集成电路的输出信号的装置和方法。 一个实施例提供了一种用于根据预定义的规范来检查信号是否由集成电路的写入电路输出的方法。 在这种情况下,系统固有的外部测试装置的高精度用于在模块内检查根据规格输出集成电路的数据信号和数据采样信号。

    APPARATUS, METHOD AND SYSTEM FOR COMPARING SAMPLE DATA WITH COMPARISON DATA
    9.
    发明申请
    APPARATUS, METHOD AND SYSTEM FOR COMPARING SAMPLE DATA WITH COMPARISON DATA 审中-公开
    用于比较采样数据与比较数据的装置,方法和系统

    公开(公告)号:US20090006785A1

    公开(公告)日:2009-01-01

    申请号:US11769874

    申请日:2007-06-28

    IPC分类号: G06F12/00

    CPC分类号: G06F11/08 G11C15/00

    摘要: An apparatus, method and system for comparing sample data with comparison date is disclosed. One embodiment provides a plurality of storage locations, an interface coupled to a plurality of storage locations for an exchange of data between the plurality of storage locations and external circuitry coupled to the interface, and a data comparator for comparing comparison data stored in the plurality of storage locations and sample data.

    摘要翻译: 公开了用于比较样本数据与比较日期的装置,方法和系统。 一个实施例提供多个存储位置,耦合到多个存储位置的接口,用于在多个存储位置之间交换数据和耦合到该接口的外部电路;以及数据比较器,用于比较存储在多个存储位置中的比较数据 存储位置和样本数据。

    Semiconductor memory with precharge control
    10.
    发明授权
    Semiconductor memory with precharge control 失效
    具有预充电控制的半导体存储器

    公开(公告)号:US06762958B2

    公开(公告)日:2004-07-13

    申请号:US10200902

    申请日:2002-07-23

    IPC分类号: G11C700

    摘要: The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are provided to which initially different potentials can be fed, which are subsequently amplified by a reference sense amplifier. The potential of one of the reference bit lines is amplified in a differential amplifier in order thereupon to cause a control device to initiate the precharge operation.

    摘要翻译: 通过预充电控制来控制半导体存储器中的非活动电平到字线的应用。 为了启动预充电操作,提供一对参考位线,其中可以馈送最初不同的电位,随后由参考读出放大器放大。 参考位线之一的电位在差分放大器中被放大,从而使控制装置启动预充电操作。