-
公开(公告)号：US20230140100A1
公开(公告)日：2023-05-04
申请号：US18089209
申请日：2022-12-27
IPC分类号： G06T3/40
摘要： A processing device is provided which includes memory and a processor. The processor is configured to receive an input image having a first resolution, generate at least one linear down-sampled version of the input image via a linear upscaling network, generate at least one non-linear down-sampled version of the input image via a non-linear upscaling network, extract a first feature map from the at least one linear down-sampled version of the input image, and extract a second feature map from the at least one non-linear down-sampled version of the input image. The processor is also configured to convert the at least one linear down-sampled version of the input image and the at least one non-linear down-sampled version of the input image into pixels of an output image having a second resolution higher than the first resolution using the first feature map and the second feature map.
-
公开(公告)号：US20230138518A1
公开(公告)日：2023-05-04
申请号：US17514776
申请日：2021-10-29
发明人： Paul J. Moyer
IPC分类号： G06F12/0891 , G06F12/084 , G06F13/16 , G06F9/30
摘要： Techniques for performing cache operations are provided. The techniques include for a memory access class, detecting a threshold number of instances in which cache lines in an exclusive state in a cache are changed to an invalid state or a shared state without being in a modified state; in response to the detecting, treating first coherence state agnostic requests for cache lines for the memory access class as requests for cache lines in a shared state; detecting a reset event for the memory access class; and in response to detecting the reset event, treating second coherence state agnostic requests for cache lines for the memory class as coherence state agnostic requests.
-
公开(公告)号：US20230136815A1
公开(公告)日：2023-05-04
申请号：US17514723
申请日：2021-10-29
IPC分类号： G06F1/08 , H03K23/00 , H03K17/693
摘要： A system and method for efficiently generating clock signals are described. In various implementations, an integrated circuit includes multiple clock frequency dividers both at its I/O boundaries and across its die. A clock frequency divider utilizes a first clock divider and a second clock divider that receive input clock signals with an initial phase difference between them. The first clock divider and the second clock divider generate output clock signals that have frequencies that are a fraction of the frequencies of the received input clock signals. The second clock divider uses a combined multiplexer and flip-flop (combined mux-flop) circuit. The combined mux-flop circuit receives a reset signal that is asserted asynchronously with respect to an input clock signal received by the second clock divider. The second clock divider generates an output clock signal that has the initial phase difference with an output clock signal of the first clock divider.
-
公开(公告)号：US11640840B2
公开(公告)日：2023-05-02
申请号：US17360958
申请日：2021-06-28
IPC分类号： G11C11/40 , G11C11/06 , G11C11/4078 , G11C11/408 , G06F12/1018 , G06F3/06 , G11C11/406 , G11C11/4076
摘要： An electronic device includes a memory having a plurality of memory rows and a memory refresh functional block that performs a victim row refresh operation. For the victim row refresh operation, the memory refresh functional block selects one or more victim memory rows that may be victims of data corruption caused by repeated memory accesses in a specified group of memory rows near each of the one or more victim memory rows. The memory refresh functional block then individually refreshes each of the one or more victim memory rows.
-
公开(公告)号：US20230129642A1
公开(公告)日：2023-04-27
申请号：US17507597
申请日：2021-10-21
摘要： A system and method for efficiently measuring on-die power supply voltage are described. In various implementations, an integrated circuit includes power supply monitors across a die of the integrated circuit. A power supply monitor receives a power supply voltage and generates a code indicating a value of the power supply voltage. A first ring oscillator receives the power supply voltage and a pulse used as an enable signal. A pulse generator of the power supply monitor takes into account the process, voltage and temperature (PVT) characteristics of the integrated circuit by including at least a second ring oscillator and a modulus counter that receives an output of the second ring oscillator. Therefore, the pulse generated by the pulse generator is PVT dependent and increases gain of the power supply monitor.
-
公开(公告)号：US11635967B2
公开(公告)日：2023-04-25
申请号：US17032307
申请日：2020-09-25
发明人： Sateesh Lagudu , Allen H. Rush , Michael Mantor , Arun Vaidyanathan Ananthanarayan , Prasad Nagabhushanamgari , Maxim V. Kazakov
摘要： An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that broadcast sets of the parameter values to mutually exclusive subsets of the rows and columns of the processor element arrays. In some cases, the array processor includes single-instruction-multiple-data (SIMD) units including subsets of the processor element arrays in corresponding rows, workgroup processors (WGPs) including subsets of the SIMD units, and a memory fabric configured to interconnect with an external memory that stores the parameter values. The memory interfaces broadcast the parameter values to the SIMD units that include the processor element arrays in rows associated with the memory interfaces and columns of processor element arrays that are implemented across the SIMD units in the WGPs. The memory interfaces access the parameter values from the external memory via the memory fabric.
-
公开(公告)号：US20230124434A1
公开(公告)日：2023-04-20
申请号：US17502272
申请日：2021-10-15
摘要： A method for operating a system including a voltage regulating power supply includes sensing a local voltage on a first node of the system and a remote voltage on a second node of the system. The first node and the second node are in a conductive path coupled to a load of the system. The first node is closer to a power stage of the voltage regulating power supply than the second node. The second node is closer to the load than the first node. The method includes detecting a load release event based on the local voltage, the remote voltage, and at least one predetermined threshold value.
-
公开(公告)号：US20230120305A1
公开(公告)日：2023-04-20
申请号：US17965888
申请日：2022-10-14
发明人： CHIA-HAO CHENG , RAHUL AGARWAL , CHINTAN BUCH , ARSALAN ALAM
IPC分类号： H01L21/66 , H01L23/48 , H01L23/00 , H01L21/463 , H01L21/465 , H01L21/3205
摘要： A method includes applying a temporary pad to a conductive pad of a semiconductor die. After testing the semiconductor die, the temporary pad is removed from the conductive pad.
-
公开(公告)号：US11630994B2
公开(公告)日：2023-04-18
申请号：US15898433
申请日：2018-02-17
IPC分类号： G06N3/08 , G06F15/173 , G06N3/084 , G06N3/063 , G06N3/045
摘要： A method of training a neural network includes, at a local computing node, receiving remote parameters from a set of one or more remote computing nodes, initiating execution of a forward pass in a local neural network in the local computing node to determine a final output based on the remote parameters, initiating execution of a backward pass in the local neural network to determine updated parameters for the local neural network, and prior to completion of the backward pass, transmitting a subset of the updated parameters to the set of remote computing nodes.
-
公开(公告)号：US11630667B2
公开(公告)日：2023-04-18
申请号：US16697660
申请日：2019-11-27
发明人： Jiasheng Chen , Bin He , Jian Huang , Michael Mantor
摘要： A processor includes a plurality of vector sub-processors (VSPs) and a plurality of memory banks dedicated to respective VSPs. A first memory bank corresponding to a first VSP includes a first plurality of high vector general purpose register (VGPR) banks and a first plurality of low VGPR banks corresponding to the first plurality of high VGPR banks. The first memory bank further includes a plurality of operand gathering components that store operands from respective high VGPR banks and low VGPR banks. The operand gathering components are assigned to individual threads while the threads are executed by the first VSP.
-
-
-
-
-
-
-
-
-
搜索结果
3564 条记录 (耗时 0.081 秒)