公开(公告)号：US08035162B2

公开(公告)日：2011-10-11

申请号：US12729040

申请日：2010-03-22

申请人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

发明人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

IPC分类号： H01L29/72

CPC分类号： H03L7/23 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L24/06 ,  H01L27/0248 ,  H01L2224/05554 ,  H01L2924/12034 ,  H01L2924/12035 ,  H01L2924/14 ,  H01L2924/3011 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。 还提供每个引脚上的分流器，以放电ESD积聚。 分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

公开(公告)号：US08013768B2

公开(公告)日：2011-09-06

申请号：US10163313

申请日：2002-06-07

申请人： Stephen A Jantzi ,  Anilkumar V Tammineedi ,  Jungwoo Song ,  Lawrence M Burns ,  Donald G McMullin ,  Agnes N Woo

发明人： Stephen A Jantzi ,  Anilkumar V Tammineedi ,  Jungwoo Song ,  Lawrence M Burns ,  Donald G McMullin ,  Agnes N Woo

IPC分类号： H03M1/66

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US07692247B2

公开(公告)日：2010-04-06

申请号：US11878750

申请日：2007-07-26

申请人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

发明人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

IPC分类号： H01L29/72

CPC分类号： H01L23/50 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/23 ,  H04B1/28 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。 还提供每个引脚上的分流器，以放电ESD积聚。 分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

公开(公告)号：US07417303B2

公开(公告)日：2008-08-26

申请号：US11521361

申请日：2006-09-15

申请人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

发明人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

IPC分类号： H01L29/72

CPC分类号： H01L23/50 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/23 ,  H04B1/28 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。 还提供每个引脚上的分流器，以放电ESD积聚。 分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

公开(公告)号：US07115952B2

公开(公告)日：2006-10-03

申请号：US11171325

申请日：2005-07-01

申请人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

发明人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

IPC分类号： H01L29/72

CPC分类号： H01L23/50 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/23 ,  H04B1/28 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programable attenuation and a programable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

公开(公告)号：US06747510B2

公开(公告)日：2004-06-08

申请号：US10163143

申请日：2002-06-07

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F152

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。

公开(公告)号：US06445039B1

公开(公告)日：2002-09-03

申请号：US09483551

申请日：2000-01-14

申请人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

发明人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

IPC分类号： H01L2972

CPC分类号： H01L23/50 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L23/60 ,  H01L27/0248 ,  H01L27/0251 ,  H01L27/08 ,  H01L2924/0002 ,  H01L2924/3011 ,  H03B5/1212 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J1/0075 ,  H03J3/04 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H03L7/23 ,  H04B1/28 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。 还提供每个引脚上的分流器，以放电ESD积聚。 分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

公开(公告)号：US08405152B2

公开(公告)日：2013-03-26

申请号：US13268386

申请日：2011-10-07

申请人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

发明人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

IPC分类号： H01L29/72

CPC分类号： H03J3/08 ,  H01L27/0251 ,  H03D1/22 ,  H03G1/0005 ,  H03H11/1291 ,  H03J2200/10 ,  H03J2200/18 ,  H03K17/164 ,  H03K2217/96015 ,  H03L7/095 ,  H03L7/18

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。

公开(公告)号：US20100172060A1

公开(公告)日：2010-07-08

申请号：US12729040

申请日：2010-03-22

申请人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

发明人： Agnes N. Woo ,  Kenneth R. Kindsfater ,  Fang Lu

IPC分类号： H02H9/02

CPC分类号： H03L7/23 ,  H01F17/0006 ,  H01F17/0013 ,  H01F2017/0053 ,  H01F2021/125 ,  H01L23/5227 ,  H01L24/06 ,  H01L27/0248 ,  H01L2224/05554 ,  H01L2924/12034 ,  H01L2924/12035 ,  H01L2924/14 ,  H01L2924/3011 ,  H03B5/364 ,  H03D7/161 ,  H03D7/18 ,  H03G1/0029 ,  H03H11/1291 ,  H03J3/08 ,  H03J3/185 ,  H03J2200/10 ,  H03L7/10 ,  H01L2924/00

摘要： An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

摘要翻译： 描述了基本上在单个CMOS集成电路上实现的具有信道选择和图像抑制的集成接收机。 接收机前端提供可编程衰减和可编程增益低噪声放大器。 频率转换电路有利地使用集成到衬底上的LC滤波器与图像抑制混合器结合，以提供足够的图像频率抑制。 过滤器调谐和电感Q补偿温度在芯片上执行。 滤波器采用多轨螺旋电感。 使用本地振荡器调整滤波器以调整替代滤波器，以及滤波器组件值期间的频率缩放与被调谐的滤波器的频率缩放。 结合滤波，频率规划提供了额外的镜像抑制。 片上本地振荡器信号产生方法的有利选择是通过PLL带外本地振荡和通过频带本地振荡器的直接合成。 PLL中的VCO使用控制电路居中，使调谐电容范围居中。 差分晶体振荡器有利地用作频率参考。 差分信号传输有利地用于整个接收机。 ESD保护由保护信号完整性的焊盘环和ESD钳位结构提供。 还提供每个引脚上的分流器，以放电ESD积聚。 分流器利用栅极升压结构来提供足够的小信号RF性能和最小的寄生负载。

公开(公告)号：US08334721B2

公开(公告)日：2012-12-18

申请号：US13226233

申请日：2011-09-06

申请人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

发明人： Stephen A. Jantzi ,  Anilkumar V. Tammineedi ,  Jungwoo Song ,  Lawrence M. Burns ,  Donald G. McMullin ,  Agnes N. Woo

IPC分类号： H03F1/14

CPC分类号： H03G3/001 ,  H03G1/0088

摘要： An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.

摘要翻译： 上游放大器集成在具有数模转换器（DAC）的基板上，以形成集成电路。 在一个实施例中，低通滤波器也集成在基板上。 上游放大器的输出信号电平是可控的。 在实施例中，通过改变DAC的偏置电流对上游放大器的输出信号电平进行微调。 软件控制位用于在上电操作模式和掉电操作模式之间切换。 上游放大器以突发模式发送。 上游放大器的功耗随放大器的输出信号电平而变化。 在上游放大器的正和负路径之间达到高度的匹配。 这提供了诸如衬底噪声，时钟刺激和由增益变化引起的毛刺等共模干扰的高抗扰性。