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公开(公告)号:US6016012A
公开(公告)日:2000-01-18
申请号:US744248
申请日:1996-11-05
申请人: Ahmad Chatila , Kuantai Yeh , James M. Cleeves , Daniel Arnzen , Roger Caldwell
发明人: Ahmad Chatila , Kuantai Yeh , James M. Cleeves , Daniel Arnzen , Roger Caldwell
IPC分类号: H01L21/768 , H01L23/522 , H01L23/532 , H01L29/43
CPC分类号: H01L21/76843 , H01L23/5226 , H01L23/53223 , H01L23/53257 , H01L2924/0002
摘要: The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.
摘要翻译: 本发明涉及包含通孔的半导体器件和在半导体器件中形成通孔的方法。
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公开(公告)号:US5897371A
公开(公告)日:1999-04-27
申请号:US769766
申请日:1996-12-19
申请人: Kuantai Yeh , Ahmad Chatila , Shahin Sharifzadeh
发明人: Kuantai Yeh , Ahmad Chatila , Shahin Sharifzadeh
IPC分类号: H01L21/321 , H01L21/4763
CPC分类号: H01L21/3212 , H01L2223/54453 , Y10S438/975
摘要: The present invention concerns a process that maintains a second (or "replica") set of alignment marks during existing processing steps used in manufacturing a semiconductor device or integrated circuit, including CMP and other planarization methods. The present invention avoids alignment problems encountered in conventional CMP processes, particularly tungsten CMP. All alignment steps can be realized through one or more subsequent second (or "replica") alignment marks, set and preserved throughout the remaining process steps, thus maintaining alignment integrity. The present method and apparatus concerns a new alignment mark that may be "printed" in a metal layer on the wafer, for example, a local interconnect or contact layer. The new alignment mark is generally not subjected to planarization or to an "open frame" process. The new alignment mark may also be used to re-etch other alignment marks directly onto the layer conventionally causing alignment problems, such as those created following CMP.
摘要翻译: 本发明涉及一种在制造半导体器件或集成电路(包括CMP和其他平面化方法)中使用的现有处理步骤期间维持第二(或“复制”)对齐标记集的方法。 本发明避免了常规CMP工艺中遇到的对准问题,特别是钨CMP。 所有对准步骤可以通过一个或多个随后的第二(或“复制”)对准标记来实现,在整个剩余的工艺步骤中设置和保持对准标记,从而保持对准完整性。 本方法和装置涉及可以“印刷”在晶片上的金属层中的新对准标记,例如局部互连或接触层。 新的对准标记通常不经受平面化或“开放框架”过程。 新的对准标记也可以用于将其它对准标记直接重新蚀刻到层上,常规地引起对准问题,例如在CMP之后产生的对准问题。
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公开(公告)号:US07355880B1
公开(公告)日:2008-04-08
申请号:US10823529
申请日:2004-04-13
申请人: Bo Jin , Ahmad Chatila , Kaichiu Wong
发明人: Bo Jin , Ahmad Chatila , Kaichiu Wong
IPC分类号: G11C11/24
CPC分类号: G11C11/4125 , H01L27/11 , H01L27/1104 , Y10S257/903
摘要: A semiconductor device memory cell (100) can include a built-in capacitor for reducing a soft-error rate (SER). A memory cell (100) can include a first inverter (102) and second inverter (104) arranged in a cross-coupled configuration. A capacitor (110) can be coupled between a first storage node (106) and second storage node (108). A capacitor (110) can be a “built-in” capacitor formed with interconnect wirings utilized to connect memory cell circuit components.
摘要翻译: 半导体器件存储单元(100)可以包括用于降低软错误率(SER)的内置电容器。 存储单元(100)可以包括以交叉耦合配置布置的第一反相器(102)和第二反相器(104)。 电容器(110)可以耦合在第一存储节点(106)和第二存储节点(108)之间。 电容器(110)可以是形成有用于连接存储器单元电路部件的互连布线的“内置”电容器。
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