公开(公告)号：US4782037A

公开(公告)日：1988-11-01

申请号：US925458

申请日：1986-10-30

申请人： Akihiro Tomozawa ,  Yoku Kaino ,  Shigeru Shimada ,  Nozomi Horino ,  Yoshiaki Yoshiura ,  Osamu Tsuchiya ,  Shozo Hosoda

发明人： Akihiro Tomozawa ,  Yoku Kaino ,  Shigeru Shimada ,  Nozomi Horino ,  Yoshiaki Yoshiura ,  Osamu Tsuchiya ,  Shozo Hosoda

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L21/441 ,  H01L21/473

CPC分类号： H01L23/5329 ,  H01L21/76889 ,  H01L23/53295 ,  H01L2924/0002

摘要： Herein disclosed is a process of fabricating a semiconductor integrated circuit device, in which there is formed between a conductive layer prepared by covering a polycrystalline silicon layer with either a layer containing a refractory metal of high melting point, i.e., a refractory metal layer or a silicide layer of the refractory metal and a first insulating film made of phosphosilicate glass flowing over said conductive layer containing the refractory metal, a second insulating film preventing the layer containing a refractory metal from peeling from the polycrystalline silicon layer by the glass flow. The second insulating film is formed by deposition to have a thickness not smaller than a predetermined value.

摘要翻译： 这里公开了一种制造半导体集成电路器件的方法，其中形成在通过将多晶硅层与含有高熔点难熔金属的层（即，难熔金属层）或 难熔金属的硅化物层和由磷硅酸盐玻璃制成的第一绝缘膜，所述第一绝缘膜流过含有难熔金属的导电层，第二绝缘膜防止含有难熔金属的层通过玻璃流从多晶硅层剥离。 通过沉积形成第二绝缘膜以具有不小于预定值的厚度。

公开(公告)号：US3935083A

公开(公告)日：1976-01-27

申请号：US431488

申请日：1974-01-07

申请人： Akihiro Tomozawa ,  Kensuke Nakata ,  Akira Kikuchi ,  Takashi Agastuma

发明人： Akihiro Tomozawa ,  Kensuke Nakata ,  Akira Kikuchi ,  Takashi Agastuma

IPC分类号： H05K3/28 ,  H01L21/283 ,  H01L21/306 ,  H01L21/768 ,  H01L23/29 ,  H01L23/522 ,  C25D5/02 ,  B01J17/00 ,  H01L23/28

CPC分类号： H01L23/291 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/09701

摘要： A method for forming an insulating film on an interconnection layer for an integrated circuit, or the like, includes the steps of forming an aluminum layer on the surface of a substrate, oxidizing a thin portion of the upper surface of the aluminum layer in order to convert the thin parts into a porous alumina film, applying a photoresist film having a predetermined pattern on the upper surface of the porous alumina film, and etching those portions of the porous alumina film, together with the aluminum layer which are not covered with the photoresist film. Then, the photoresist film is removed and an aluminum film is formed on the entire surface of the resulting substrate; the aluminum film is oxidized, to form a porous alumina film, and the surface of the remaining aluminum layer is anodized, in order to form a non-porous alumina film. Finally, unnecessary portions of the remaining porous alumina film are removed, and a film is formed by chemical vapor deposition on the resulting structure.

摘要翻译： 在集成电路等的互连层上形成绝缘膜的方法包括以下步骤：在基板的表面上形成铝层，氧化铝层的上表面的薄部分，以便 将薄部分转化为多孔氧化铝膜，在多孔氧化铝膜的上表面上涂布具有预定图案的光致抗蚀剂膜，并将多孔氧化铝膜的那些部分与未被光致抗蚀剂覆盖的铝层一起蚀刻 电影。 然后，去除光致抗蚀剂膜，并在所得基板的整个表面上形成铝膜; 铝膜被氧化，形成多孔氧化铝膜，并且将其余的铝层的表面进行阳极氧化，以便形成无孔氧化铝膜。 最后，除去剩余的多孔氧化铝膜的不需要的部分，并通过化学气相沉积在所得到的结构上形成膜。

公开(公告)号：US4014718A

公开(公告)日：1977-03-29

申请号：US609604

申请日：1975-09-02

申请人： Akihiro Tomozawa ,  Takanori Nishimura ,  Takashi Yamaguchi

发明人： Akihiro Tomozawa ,  Takanori Nishimura ,  Takashi Yamaguchi

IPC分类号： H01L29/73 ,  H01L21/28 ,  H01L21/331 ,  H01L21/761 ,  H01L21/8222 ,  H01L27/02 ,  H01L21/22

CPC分类号： H01L27/0248 ,  H01L21/8222

摘要： In order to prevent the formation of a parasitic PNPN thyristor in an integrated circuit having at least one NPN transistor, a layer of semiconductor material of a conductivity type opposite that of the substrate is formed on the substrate. An isolation region of the same conductivity type as the substrate is formed on this layer and a further layer of the same conductivity type as the isolation region, but of a higher impurity concentration, is formed on the back surface of the substrate. A diffusion layer of the same conductivity type as the substrate, which serves as the base region of the NPN transistor, is formed on the layer having the conductivity type opposite to that of the substrate. A further layer of the same conductivity type and a higher impurity concentration than the isolation region is formed on the back surface of the substrate and an insolation layer is formed on the back surface of the substrate and on the substrate. A further diffusion layer of a conductivity type opposite to that of the substrate, which serves as the emitter region of the transistor is formed using the insolation layer as a mask.

摘要翻译： 为了防止在具有至少一个NPN晶体管的集成电路中形成寄生PNPN晶闸管，在衬底上形成导电类型与衬底相反的半导体材料层。 在该层上形成与衬底相同的导电类型的隔离区，并且在衬底的背面上形成与隔离区相同的导电类型但具有较高杂质浓度的另一层。 与作为NPN晶体管的基极区域的与衬底相同的导电类型的扩散层形成在具有与衬底相反的导电类型的层上。 在基板的背面上形成与隔离区相同的导电类型和较高的杂质浓度的另一层，并且在基板的背面和基板上形成隔离层。 使用日照层作为掩模，形成与作为晶体管的发射极区域的衬底相反的导电类型的另一个扩散层。

公开(公告)号：US4377819A

公开(公告)日：1983-03-22

申请号：US032017

申请日：1979-04-20

申请人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki ,  Hisao Katto ,  Norikazu Hashimoto ,  Shin-ichi Muramatsu ,  Akihiro Tomozawa

发明人： Yoshio Sakai ,  Toshiaki Masuhara ,  Osamu Minato ,  Toshio Sasaki ,  Hisao Katto ,  Norikazu Hashimoto ,  Shin-ichi Muramatsu ,  Akihiro Tomozawa

IPC分类号： G11C11/412 ,  H01L21/02 ,  H01L21/318 ,  H01L21/822 ,  H01L27/04 ,  H01L27/06 ,  H01L27/11 ,  H01L29/06 ,  H01L29/40 ,  H01L29/41 ,  H01L29/04

CPC分类号： H01L29/402 ,  H01L21/3185 ,  H01L27/0605 ,  H01L27/1112 ,  H01L28/20 ,  H01L29/41

摘要： A semiconductor device including at least a resistance element formed of polycrystalline silicon having a high resistivity. An electrode is provided on the high resistance polycrystalline silicon region with a silicon dioxide film and a silicon nitride film being interposed therebetween. The electrode is coupled to the ground potential. In this manner, high stability is obtained in the behavior of the resistance element inasmuch as the formation of a parasitic MOS device under said high resistance region is suppressed, and the threshold voltage of any such MOS device is made raised.

摘要翻译： 一种半导体器件，至少包括由具有高电阻率的多晶硅形成的电阻元件。 在具有二氧化硅膜的高电阻多晶硅区域上设置电极，并且在其间插入有氮化硅膜。 电极与地电位耦合。 以这种方式，由于抑制了在所述高电阻区域下的寄生MOS器件的形成，所以电阻元件的性能得到了很高的稳定性，并且提高了任何这种MOS器件的阈值电压。

公开(公告)号：US3972756A

公开(公告)日：1976-08-03

申请号：US400924

申请日：1973-09-26

申请人： Akira Nagase ,  Masayasu Tsunematsu ,  Norio Anzai ,  Akihiro Tomozawa

发明人： Akira Nagase ,  Masayasu Tsunematsu ,  Norio Anzai ,  Akihiro Tomozawa

IPC分类号： H01L29/78 ,  H01L21/00 ,  H01L21/308 ,  H01L21/336 ,  H01L29/00 ,  H01L7/50

CPC分类号： H01L29/00 ,  H01L21/00 ,  H01L21/308 ,  H01L29/66477 ,  Y10S148/051 ,  Y10S148/053 ,  Y10S148/106

摘要： A method of producing an MIS structure having self-alignment construction, wherein an insulating film is formed on the surface of a semiconductor substrate, a semiconductor layer is formed on a selected area of the insulating film, parts of the insulating film are etched using the semiconductor layer as a mask, and the surface of the semiconductor layer is etched in such manner that the underlying insulating film may not be etched, whereby the marginal portion of the semiconductor layer which otherwise projects laterally beyond the underlying insulating film is caused to recede.

摘要翻译： 一种制造具有自对准结构的MIS结构的方法，其中在半导体衬底的表面上形成绝缘膜，在绝缘膜的选定区域上形成半导体层，使用 半导体层作为掩模，并且半导体层的表面被蚀刻，使得下面的绝缘膜可能不被蚀刻，由此导致横向延伸超过下面的绝缘膜的半导体层的边缘部分后退。