公开(公告)号：US10541029B2

公开(公告)日：2020-01-21

申请号：US13564458

申请日：2012-08-01

申请人： Peter Sean Feeley ,  Koji Sakui ,  Akira Goda

发明人： Peter Sean Feeley ,  Koji Sakui ,  Akira Goda

IPC分类号： G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/16

摘要： Methods and apparatuses are disclosed, such as those including a block of memory cells that includes strings of charge storage devices. Each of the strings may comprise a plurality of charge storage devices formed in a plurality of tiers. The apparatus may comprise a plurality of access lines shared by the strings. Each of the plurality of access lines may be coupled to the charge storage devices corresponding to a respective tier of the plurality of tiers. The apparatus may comprise a plurality of sub-sources associated with the strings. Each of the plurality of sub-sources may be coupled to a source select gate of each string of a respective subset of a plurality of subsets of the strings, and each sub-source may be independently selectable from other sub-sources to select the strings of its respective subset independently of other strings corresponding to other subsets.

公开(公告)号：US20180286483A1

公开(公告)日：2018-10-04

申请号：US15477048

申请日：2017-04-01

申请人： Akira Goda ,  Tommaso Vali ,  Carmine Miccoli ,  Pranav Kalavade

发明人： Akira Goda ,  Tommaso Vali ,  Carmine Miccoli ,  Pranav Kalavade

IPC分类号： G11C16/04 ,  G11C16/34 ,  G11C16/12 ,  G11C8/08

CPC分类号： G11C16/0483 ,  G11C8/08 ,  G11C11/5628 ,  G11C16/10 ,  G11C16/12 ,  G11C16/3459 ,  G11C2211/5621

摘要： Technology for a memory device operable to program memory cells in the memory device is described. The memory device can include a plurality of memory cells and a memory controller. The memory controller can perform a first programming pass to program a memory cell in the plurality of memory cells. A defined number of blanket programming pulses can be applied to the memory cell during the first programming pass. The blanket programming pulses may not include verify operations. The memory controller can perform a second programming pass to program the memory cell. A defined number of program and verify (PV) pulses can be applied to the memory cell during the second programming pass.

公开(公告)号：US20150378815A1

公开(公告)日：2015-12-31

申请号：US14314663

申请日：2014-06-25

申请人： Akira Goda ,  Pranav Kalavade ,  Charan Srinivasan

发明人： Akira Goda ,  Pranav Kalavade ,  Charan Srinivasan

IPC分类号： G06F11/10

CPC分类号： G06F11/1068 ,  G06F11/1072 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/3454 ,  G11C2029/0411

摘要： Technology for programming a page of memory in a NAND memory device is disclosed and described. In an example, a method may include applying initial programming pulses for lower page programming of the page and pre-reading data of the lower page. The method may further include determining whether to apply an error recovery operation to the data of the lower page. Data indicative of secondary programming pulses to be used for programming upper page data are stored and the upper page data is programmed based on the secondary programming pulses and the data of the lower page.

摘要翻译： 公开并描述了用于对NAND存储器件中的存储器页进行编程的技术。 在一个示例中，方法可以包括应用用于页面的较低页面编程和下部页面的预读数据的初始编程脉冲。 该方法还可以包括确定是否对下部页面的数据应用错误恢复操作。 存储表示用于编程上页数据的辅助编程脉冲的数据，并且基于次要编程脉冲和下部页面的数据对高位页数据进行编程。

公开(公告)号：US08565018B2

公开(公告)日：2013-10-22

申请号：US13486028

申请日：2012-06-01

申请人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

发明人： Akira Goda ,  Alessandro Torsi ,  Carlo Musilli ,  Mark A. Helm ,  Doyle Rivers

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/0483 ,  G11C16/14

摘要： A method for programming includes initially biasing a subset of a plurality of control gates of a string of memory cells with a negative voltage, wherein the subset is less than all of the plurality of control gates of the string. The control gate of a selected memory cell is subsequently biased with a programming voltage during a programming phase.

摘要翻译： 一种用于编程的方法包括：初始地利用负电压偏置存储器单元串的多个控制栅极的子集，其中所述子集小于所述串的所述多个控制栅极的全部。 在编程阶段期间，所选择的存储单元的控制栅随后用编程电压进行偏置。

公开(公告)号：US20130044549A1

公开(公告)日：2013-02-21

申请号：US13210194

申请日：2011-08-15

申请人： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

发明人： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC分类号： G11C16/04 ,  H01L29/78 ,  H01L29/788

CPC分类号： G11C16/0483 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

摘要： Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

摘要翻译： 公开了装置和方法，例如包括与柱（例如半导体材料）相关联的一串电荷存储装置的装置，源极栅极装置和耦合在源栅极装置和串之间的源极选择装置。 描述附加的装置和方法。

公开(公告)号：US08374028B2

公开(公告)日：2013-02-12

申请号：US13009540

申请日：2011-01-19

申请人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

发明人： Yijie Zhao ,  Akira Goda ,  Mark A. Helm

IPC分类号： G11C16/00

CPC分类号： G11C16/04 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3422 ,  G11C2211/5641

摘要： Methods for sensing and memory devices are disclosed. One such method for sensing determines a threshold voltage of an n-bit memory cell that is adjacent to an m-bit memory cell to be sensed. A control gate of the m-bit memory cell to be sensed is biased with a sense voltage adjusted responsive to the determined threshold voltage of the n-bit memory cell.

摘要翻译： 公开了用于感测和存储器件的方法。 一种用于感测的方法确定与要感测的m位存储器单元相邻的n位存储器单元的阈值电压。 要感测的m位存储器单元的控制栅极利用响应于所确定的n位存储单元的阈值电压而调整的感测电压进行偏置。

公开(公告)号：US08369158B2

公开(公告)日：2013-02-05

申请号：US12646136

申请日：2009-12-23

申请人： Akira Goda ,  Giuseppina Puzzilli

发明人： Akira Goda ,  Giuseppina Puzzilli

IPC分类号： G11C11/34

CPC分类号： G11C16/16

摘要： Erase operations and apparatus configured to perform the erase operations are suitable for non-volatile memory devices having memory cells arranged in strings. One such method includes biasing select gate control lines of a string of memory cells to a first bias potential, biasing access lines of a pair of the memory cells to a second bias potential and biasing access lines of one or more remaining memory cells to a third potential. A ramping bias potential is applied to channel regions of the string of memory cells substantially concurrently with or subsequent to biasing the select gate control lines and the access lines, and floating the select gate control lines in response to the ramping bias potential reaching a release bias potential between an initial bias potential of the ramping bias potential and a target bias potential of the ramping bias potential.

摘要翻译： 配置为执行擦除操作的擦除操作和装置适用于具有排列成串的存储单元的非易失性存储器件。 一种这样的方法包括将一串存储器单元的选择栅极控制线偏置到第一偏置电位，将一对存储器单元的访问线偏置到第二偏置电位，并将一个或多个剩余存储器单元的访问线偏置到第三偏置电位 潜在。 斜坡偏置电位基本上与偏置选择栅极控制线和接入线的同时或之后施加到存储器单元串的沟道区，并且响应于斜坡偏置电位达到释放偏压而浮动选择栅极控制线 斜坡偏置电位的初始偏置电位与斜坡偏置电位的目标偏置电位之间的电位。

公开(公告)号：US20120327713A1

公开(公告)日：2012-12-27

申请号：US13165416

申请日：2011-06-21

申请人： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

发明人： Krishna K. Parat ,  Akira Goda ,  Koichi Kawai ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

IPC分类号： G11C16/16 ,  G11C16/04

CPC分类号： G11C29/765 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/349 ,  G11C29/789

摘要： Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

摘要翻译： 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。

公开(公告)号：US20120327712A1

公开(公告)日：2012-12-27

申请号：US13602762

申请日：2012-09-04

申请人： Akira Goda ,  Andrei Mihnea

发明人： Akira Goda ,  Andrei Mihnea

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/06 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/10 ,  G11C2211/5621 ,  G11C2211/5634

摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for operating memory cells. One method includes: performing an erase operation on a selected group of memory cells, the selected group including a number of reference cells and a number of data cells; performing a programming monitor operation on the number of reference cells as part of the erase operation; and determining a number of particular operating parameters associated with operating the number of data cells at least partially based on the programming monitor operation performed on the number of reference cells.

摘要翻译： 本公开的实施例提供用于操作存储器单元的方法，设备，模块和系统。 一种方法包括：对所选择的一组存储器单元执行擦除操作，所选择的组包括多个参考单元和多个数据单元; 对作为擦除操作的一部分的参考单元的数量进行编程监视操作; 以及至少部分地基于对参考单元的数量执行的编程监视操作来确定与操作所述数据单元的数量相关联的特定操作参数的数量。

公开(公告)号：US08253182B2

公开(公告)日：2012-08-28

申请号：US12588203

申请日：2009-10-07

申请人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

发明人： Minori Kajimoto ,  Mitsuhiro Noguchi ,  Akira Goda

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  H01L21/76838 ,  H01L27/115 ,  H01L27/11521

摘要： A nonvolatile semiconductor memory includes a first semiconductor layer; second semiconductor regions formed on the first semiconductor layer having device isolating regions extended in a column direction; a first interlayer insulator film formed above the first semiconductor layer; a lower conductive plug connected to the second semiconductor regions; a first interconnect extended in a row direction; a second interlayer insulator formed on the lower conductive plug and the first interlayer insulator film; an upper conductive plug; and a second interconnect formed on the second interlayer insulator contacting with the top of the upper conductive plug extended in the column direction.

摘要翻译： 非易失性半导体存储器包括：第一半导体层; 形成在第一半导体层上的第二半导体区域，具有沿列方向延伸的器件隔离区域; 形成在所述第一半导体层上方的第一层间绝缘膜; 连接到第二半导体区域的下导电插塞; 沿行方向延伸的第一互连; 形成在下导电插塞和第一层间绝缘膜上的第二层间绝缘膜; 上导电插头; 以及形成在与沿列方向延伸的上导电插塞的顶部接触的第二层间绝缘体上的第二互连。