公开(公告)号：US08823012B2

公开(公告)日：2014-09-02

申请号：US13403400

申请日：2012-02-23

申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao ,  Robert Strittmatter ,  Fang Chang Liu

发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao ,  Robert Strittmatter ,  Fang Chang Liu

IPC分类号： H01L21/48 ,  H01L21/02 ,  H01L29/20 ,  H01L33/00

CPC分类号： H01L21/0254 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/7786 ,  H01L33/007

摘要： Enhancement-mode GaN devices having a gate spacer, a gate metal material and a gate compound that are self-aligned, and a methods of forming the same. The materials are patterned and etched using a single photo mask, which reduces manufacturing costs. An interface of the gate spacer and the gate compound has lower leakage than the interface of a dielectric film and the gate compound, thereby reducing gate leakage. In addition, an ohmic contact metal layer is used as a field plate to relieve the electric field at a doped III-V gate compound corner towards the drain contact, which leads to lower gate leakage current and improved gate reliability.

摘要翻译： 具有栅极间隔物，栅极金属材料和自对准的栅极化合物的增强型GaN器件及其形成方法。 使用单个光掩模对材料进行图案化和蚀刻，这降低了制造成本。 栅极间隔物和栅极化合物的界面比电介质膜和栅极化合物的界面具有更低的泄漏，从而减少栅极泄漏。 此外，使用欧姆接触金属层作为场板，以减轻掺杂III-V栅极化合物角向漏极接触的电场，这导致较低的栅极漏电流和改善的栅极可靠性。

公开(公告)号：US20100258848A1

公开(公告)日：2010-10-14

申请号：US12756906

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Jianjun Cao ,  Alana Nakata ,  Guang Yuan Zhao

发明人： Alexander Lidow ,  Robert Beach ,  Jianjun Cao ,  Alana Nakata ,  Guang Yuan Zhao

IPC分类号： H01L29/78 ,  H01L29/772

CPC分类号： H01L29/802 ,  H01L29/2003 ,  H01L29/66522

摘要： A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.

摘要翻译： 具有低栅极泄漏的MISFET，例如GaN晶体管。 在一个实施例中，栅极泄漏随着栅极接触下方的补偿GaN层和势垒层上方而减小。 在另一个实施例中，通过在栅极接触之下和阻挡层之上采用半绝缘层来减小栅极泄漏。

公开(公告)号：US20100258844A1

公开(公告)日：2010-10-14

申请号：US12756975

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao

发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao

IPC分类号： H01L29/772 ,  H01L23/367 ,  H01L23/488

CPC分类号： H01L23/3192 ,  H01L23/3178 ,  H01L23/367 ,  H01L23/3672 ,  H01L24/13 ,  H01L24/16 ,  H01L29/0657 ,  H01L29/205 ,  H01L29/267 ,  H01L29/41725 ,  H01L29/7787 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2224/05599 ,  H01L2224/05099

摘要： A semiconductor device comprising a silicon substrate, a compound semiconductor material, an insulating material between the silicon substrate and the compound semiconductor material, and a top surface comprising means of electrical connection, and passivation material, where the passivation material is silicon nitride, silicon dioxide, or a combination of both. The present invention eliminates the need for a thick electrical insulator between a heat sink and the back surface of a surface mounted device by the inclusion of an AlN seed layer to electrically isolate the silicon substrate of the device. The sidewalls of the device are also electrically isolated from the active area of the device.

摘要翻译： 一种半导体器件，包括硅衬底，化合物半导体材料，硅衬底和化合物半导体材料之间的绝缘材料，以及包括电连接装置的顶表面和钝化材料，其中钝化材料是氮化硅，二氧化硅 ，或两者的组合。 本发明通过包含AlN晶种层来电绝缘器件的硅衬底，消除了散热器与表面安装器件背面之间的厚电绝缘体的需要。 器件的侧壁也与器件的有源区域电隔离。

公开(公告)号：US08853749B2

公开(公告)日：2014-10-07

申请号：US13362669

申请日：2012-01-31

申请人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Robert Strittmatter ,  Guang Y. Zhao ,  Alana Nakata

发明人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Robert Strittmatter ,  Guang Y. Zhao ,  Alana Nakata

IPC分类号： H01L29/76 ,  H01L21/336 ,  H01L29/423 ,  H01L29/778 ,  H01L29/66 ,  H01L21/265 ,  H01L29/20

CPC分类号： H01L21/26586 ,  H01L21/26546 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

摘要： A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer.

摘要翻译： 一种自对准的晶体管栅极结构，其包括在每侧由非植入栅极材料包围的栅极材料的离子注入部分。 栅极结构可以例如通过在AlGaN阻挡层上施加GaN材料层并且注入GaN层的一部分以形成由GaN层横向包围的栅极结构来形成。

公开(公告)号：US08350294B2

公开(公告)日：2013-01-08

申请号：US12756906

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Jianjun Cao ,  Alana Nakata ,  Guang Yuan Zhao

发明人： Alexander Lidow ,  Robert Beach ,  Jianjun Cao ,  Alana Nakata ,  Guang Yuan Zhao

IPC分类号： H01L29/66

CPC分类号： H01L29/802 ,  H01L29/2003 ,  H01L29/66522

摘要： A MISFET, such as a GaN transistor, with low gate leakage. In one embodiment, the gate leakage is reduced with a compensated GaN layer below the gate contact and above the barrier layer. In another embodiment, the gate leakage is reduced by employing a semi-insulating layer below the gate contact and above the barrier layer.

摘要翻译： 具有低栅极泄漏的MISFET，例如GaN晶体管。 在一个实施例中，栅极泄漏随着栅极接触下方的补偿GaN层和势垒层上方而减小。 在另一个实施例中，通过在栅极接触之下和阻挡层之上采用半绝缘层来减小栅极泄漏。

公开(公告)号：US09607876B2

公开(公告)日：2017-03-28

申请号：US13325735

申请日：2011-12-14

申请人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Johan Strydom ,  Alana Nakata ,  Guang Y. Zhao

发明人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Johan Strydom ,  Alana Nakata ,  Guang Y. Zhao

IPC分类号： H01L21/74 ,  H01L21/761 ,  H01L21/762 ,  H01L29/732 ,  H01L29/778 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/06 ,  H01L27/085 ,  H01L29/20

CPC分类号： H01L21/743 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/8252 ,  H01L21/8258 ,  H01L23/535 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/085 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/732 ,  H01L29/7786 ,  H01L29/7787 ,  H01L29/7827 ,  H01L29/88 ,  H01L2924/0002 ,  H01L2924/00

摘要： Circuits, structures and techniques for independently connecting a surrounding material in a part of a semiconductor device to a contact of its respective device. To achieve this, a combination of one or more conductive wells that are electrically isolated in at least one bias polarity are provided.

公开(公告)号：US08969918B2

公开(公告)日：2015-03-03

申请号：US12756940

申请日：2010-04-08

申请人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

发明人： Alexander Lidow ,  Robert Beach ,  Alana Nakata ,  Jianjun Cao ,  Guang Yuan Zhao

IPC分类号： H01L29/66 ,  H01L29/778 ,  H01L29/10 ,  H01L29/20

CPC分类号： H01L29/7787 ,  H01L29/1066 ,  H01L29/2003

摘要： An enhancement mode GaN transistor having a gate pGaN structure having a thickness which avoids dielectric failure. In one embodiment, this thickness is in the range of 400 Å to 900 Å. In a preferred embodiment, the thickness is 600 Å.

摘要翻译： 具有栅极pGaN结构的增强型GaN晶体管，具有避免电介质破坏的厚度。 在一个实施例中，该厚度在400至900的范围内。 在优选实施例中，厚度为600埃。

公开(公告)号：US20120193688A1

公开(公告)日：2012-08-02

申请号：US13362669

申请日：2012-01-31

申请人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Robert Strittmatter ,  Guang Y. Zhao ,  Alana Nakata

发明人： Alexander Lidow ,  Jianjun Cao ,  Robert Beach ,  Robert Strittmatter ,  Guang Y. Zhao ,  Alana Nakata

IPC分类号： H01L29/768 ,  H01L21/336

CPC分类号： H01L21/26586 ,  H01L21/26546 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/7787

摘要： A self-aligned transistor gate structure that includes an ion-implanted portion of gate material surrounded by non-implanted gate material on each side. The gate structure may be formed, for example, by applying a layer of GaN material over an AlGaN barrier layer and implanting a portion of the GaN layer to create the gate structure that is laterally surrounded by the GaN layer.

摘要翻译： 一种自对准的晶体管栅极结构，其包括在每侧由非植入栅极材料包围的栅极材料的离子注入部分。 栅极结构可以例如通过在AlGaN阻挡层上施加GaN材料层并且注入GaN层的一部分以形成由GaN层横向包围的栅极结构来形成。

公开(公告)号：US20090279220A1

公开(公告)日：2009-11-12

申请号：US12115761

申请日：2008-05-06

申请人： Henning M. Hauenstein ,  Alana Nakata

发明人： Henning M. Hauenstein ,  Alana Nakata

IPC分类号： H02H9/02

CPC分类号： H01L23/495 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49589 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/85447 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integral impedence is formed on or within a lead frame pin of a semiconductor package and receives a connection from an electrode of a semiconductor die within the package to eliminate the need for adjustment and protective impedences external of the package. The impedence comprises passives such as resistors, capacitors, diodes or inductors which modify the performance of the package for new semiconductor device characteristics. The impedences may have positive or negative temperature coefficients and are in close thermal communication with the semiconductor die.

摘要翻译： 整体阻抗形成在半导体封装的引线框架引脚上或内部，并且在封装内接收来自半导体管芯的电极的连接，以消除对封装外部的调整和保护阻抗的需要。 阻抗包括诸如电阻器，电容器，二极管或电感器的无源器件，其改变了用于新的半导体器件特性的封装的性能。 阻抗可以具有正或负温度系数，并且与半导体管芯紧密地热连通。

公开(公告)号：US08102668B2

公开(公告)日：2012-01-24

申请号：US12115761

申请日：2008-05-06

申请人： Henning M. Hauenstein ,  Alana Nakata

发明人： Henning M. Hauenstein ,  Alana Nakata

IPC分类号： H05K7/10

CPC分类号： H01L23/495 ,  H01L23/3107 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49589 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05647 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48472 ,  H01L2224/48647 ,  H01L2224/48747 ,  H01L2224/49109 ,  H01L2224/49113 ,  H01L2224/85447 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integral impedence is formed on or within a lead frame pin of a semiconductor package and receives a connection from an electrode of a semiconductor die within the package to eliminate the need for adjustment and protective impedences external of the package. The impedence comprises passives such as resistors, capacitors, diodes or inductors which modify the performance of the package for new semiconductor device characteristics. The impedences may have positive or negative temperature coefficients and are in close thermal communication with the semiconductor die.

摘要翻译： 整体阻抗形成在半导体封装的引线框架引脚上或内部，并且在封装内接收来自半导体管芯的电极的连接，以消除对封装外部的调整和保护阻抗的需要。 阻抗包括诸如电阻器，电容器，二极管或电感器的无源器件，其改变了用于新的半导体器件特性的封装的性能。 阻抗可以具有正或负温度系数，并且与半导体管芯紧密地热连通。