公开(公告)号：US08259888B2

公开(公告)日：2012-09-04

申请号：US12153803

申请日：2008-05-23

申请人： Junqi Hua ,  Alberto Baldisserotto ,  Steven White

发明人： Junqi Hua ,  Alberto Baldisserotto ,  Steven White

IPC分类号： H03D3/24

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/099 ,  H04L7/0025 ,  H04L7/033

摘要： The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained.

摘要翻译： 本发明提供一种处理信号数据的方法，包括产生第一时钟信号和第二时钟信号，并使用第一时钟信号和第二时钟信号对信号数据进行处理。 在处理信号数据的同时，对第一时钟信号和第二时钟信号之间的相位差进行测量和校正，以便保持第一时钟信号和第二时钟信号之间的目标相位差。

公开(公告)号：US20090289672A1

公开(公告)日：2009-11-26

申请号：US12153803

申请日：2008-05-23

申请人： Junqi Hua ,  Alberto Baldisserotto ,  Steven White

发明人： Junqi Hua ,  Alberto Baldisserotto ,  Steven White

IPC分类号： H03L7/087

CPC分类号： H03L7/0812 ,  H03L7/07 ,  H03L7/099 ,  H04L7/0025 ,  H04L7/033

摘要： The present invention provides a method of processing signal data comprising generating a first clock signal and a second clock signal and processing the signal data using the first clock signal and the second clock signal. While processing the signal data, the phase difference between the first clock signal and the second clock signal is measured and corrected for so that a target phase difference between the first clock signal and the second clock signal is maintained.

摘要翻译： 本发明提供一种处理信号数据的方法，包括产生第一时钟信号和第二时钟信号，并使用第一时钟信号和第二时钟信号对信号数据进行处理。 在处理信号数据的同时，对第一时钟信号和第二时钟信号之间的相位差进行测量和校正，以便保持第一时钟信号和第二时钟信号之间的目标相位差。

公开(公告)号：US20090289668A1

公开(公告)日：2009-11-26

申请号：US12153792

申请日：2008-05-23

申请人： Alberto Baldisserotto ,  Steven Broome ,  Jason Thurston ,  Carl Thomas Gray

发明人： Alberto Baldisserotto ,  Steven Broome ,  Jason Thurston ,  Carl Thomas Gray

IPC分类号： H03K3/00

CPC分类号： H03K19/018528 ,  H03K19/09432

摘要： An integrated circuit 2 is provided with an output driver circuit 12. The output driver circuit 12 one side provides between a first power supply 20 and a second power supply 18 a first transistor 16, a first output 22, a first resistor 14 and, connected in parallel with the first resistor 14, a first bypass transistor 24. The first bypass transistor 24 is controlled by a first bypass control voltage vbp such that as the first output voltage of the first output 22 approaches the second power supply voltage of the second power supply 18, the first bypass transistor 24 serves to bypass the first resistor 14 and provide a single-ended impedance of the output driver circuit 12 which approximates to zero. On the complementary side of the output driver circuit 12 there are similarly provided a second transistor 28, a second resistor 26 and a bypass transistor 32.

摘要翻译： 集成电路2设置有输出驱动器电路12.输出驱动器电路12一侧提供第一电源20和第二电源18之间的第一晶体管16，第一输出22，第一电阻14和连接 与第一电阻器14并联，第一旁路晶体管24.第一旁路晶体管24由第一旁路控制电压vbp控制，使得当第一输出端22的第一输出电压接近第二电源的第二电源电压时 电源18，第一旁路晶体管24用于旁路第一电阻器14，并提供近似为零的输出驱动器电路12的单端阻抗。 在输出驱动器电路12的互补侧，类似地提供第二晶体管28，第二电阻26和旁路晶体管32。

公开(公告)号：US06664814B1

公开(公告)日：2003-12-16

申请号：US10199749

申请日：2002-07-18

申请人： William P. Evans ,  Luca Ravezzi ,  Alberto Baldisserotto

发明人： William P. Evans ,  Luca Ravezzi ,  Alberto Baldisserotto

IPC分类号： H03K522

CPC分类号： H03K19/018514 ,  H03K19/018585 ,  H04L25/0276 ,  H04L25/028

摘要： A circuit and method for driving the output signal, having a common-mode voltage and an output swing, of an integrated circuit. In accordance with an aspect of an embodiment of the present invention, a first power supply provides the termination voltage for the output signal and a second power supply provides the power to set the common mode voltage. In accordance with another aspect, the common-mode voltage and the output swing are programmable.

摘要翻译： 一种用于驱动具有集成电路的共模电压和输出摆幅的输出信号的电路和方法。 根据本发明的实施例的一个方面，第一电源为输出信号提供终止电压，第二电源提供设定共模电压的电力。 根据另一方面，共模电压和输出摆幅是可编程的。