公开(公告)号：US20130019132A1

公开(公告)日：2013-01-17

申请号：US13183471

申请日：2011-07-15

申请人： Karen AMIRKHANYAN ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

发明人： Karen AMIRKHANYAN ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

IPC分类号： G11C29/10 ,  G06F11/263

CPC分类号： G11C29/08 ,  G11C11/41 ,  G11C29/10

摘要： A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

摘要翻译： 一种用于测试电子存储器的方法和系统。 该方法包括使电子存储器经受预定的一组测试条件的第一测试条件。 该方法还包括使用预定的测试算法对于第一测试条件首次多次测试电子存储器的功能。 该方法还包括如果电子存储器的功能是令人满意的，则从预定的测试条件组检查第二测试条件的可用性。 此外，该方法包括如果第二测试条件可用，则使用预定测试算法来测试第二测试条件的电子存储器的功能，第二多次。 此外，如果电子存储器的功能令人满意，则该方法包括接受用于产品的电子存储器。

公开(公告)号：US06744661B1

公开(公告)日：2004-06-01

申请号：US10146523

申请日：2002-05-15

申请人： Alex Shubat

发明人： Alex Shubat

IPC分类号： G11C1100

CPC分类号： G11C11/412

摘要： A static memory cell having reduced susceptibility to soft error events, wherein data storage nodes are hardened by way of junction isolation. The memory cell is comprised of a pair of cross-coupled inverters. A first inverter is formed with a first N-channel Metal Oxide Semiconductor (NMOS) device and a first P-channel MOS (PMOS) device, with a first isolation device disposed therebetween. A second inverter is cross-coupled to the first inverter to form a pair of data storage nodes therein. The second inverter is also provided with a second isolation device disposed between its pair of NMOS and PMOS devices. A first data storage node is formed at a coupling between the first PMOS device and the first isolation device and a second data storage node is formed at a coupling between the second PMOS device and the second isolation device.

摘要翻译： 静态存储单元对软错误事件的敏感度降低，其中数据存储节点通过结隔离来硬化。 存储单元由一对交叉耦合的反相器组成。 第一反相器由第一N沟道金属氧化物半导体（NMOS）器件和第一P沟道MOS（PMOS）器件形成，其间设置有第一隔离器件。 第二反相器与第一反相器交叉耦合以在其中形成一对数据存储节点。 第二反相器还设置有设置在其一对NMOS和PMOS器件之间的第二隔离器件。 第一数据存储节点形成在第一PMOS器件和第一隔离器件之间的耦合处，并且第二数据存储节点形成在第二PMOS器件与第二隔离器件之间的耦合处。

公开(公告)号：US06363020B1

公开(公告)日：2002-03-26

申请号：US09455045

申请日：1999-12-06

申请人： Alex Shubat ,  Chang Hee Hong

发明人： Alex Shubat ,  Chang Hee Hong

IPC分类号： G11C700

CPC分类号： G11C29/848 ,  G11C29/785 ,  G11C29/802

摘要： A semiconductor memory architecture for embedded memory instances having redundancy. A fuse box register is provided outside the memory macro associated with the memory instances. The memory instances are daisy-chained to the fuse box register containing a plurality of fuses used for storing fuse data associated with the defective rows and columns of main memory. During power-up or after blowing the fuses, the contents of the fuses (i.e., fuse data) are transferred to a plurality of volatile redundancy scan flip-flops. The fuse box is then deactivated to eliminate quiescent current through the fuses. The redundancy scan flip-flops, connected in a scan chain, are located inside the fuse box as well as the memory instances. During the shifting mode of operation, the fuse contents are scanned into individual flip-flops, organized as scan registers for row redundancy and column redundancy, of the memory instances. Redundant elements are pre-tested by bypassing the fuses and directly scanning in arbitrary patterns into the redundancy scan flip-flops (override mode operation). The contents of row redundancy scan register (i.e., faulty wordline address information) are compared with an incoming wordline address and if there is a match found, the primary wordline or wordlines are de-selected and the redundant wordline or wordlines are selected.

摘要翻译： 一种具有冗余性的嵌入式存储器实例的半导体存储器架构。 在与存储器实例相关联的存储器宏之外提供保险丝盒寄存器。 存储器实例被菊花链连接到保险丝盒寄存器，其包含用于存储与主存储器的有缺陷行和列相关联的熔丝数据的多个熔丝。 在上电期间或在熔断保险丝之后，保险丝（即，熔丝数据）的内容被传送到多个易失性冗余扫描触发器。 然后禁用保险丝盒以消除通过保险丝的静态电流。 连接在扫描链中的冗余扫描触发器位于保险丝盒内部以及存储器实例中。 在移动操作模式期间，熔丝内容被扫描到单独的触发器中，被组织为存储器实例的行冗余和列冗余的扫描寄存器。 冗余元件通过旁路保险丝并以任意图案直接扫描到冗余扫描触发器（覆盖模式操作）中进行预测试。 将行冗余扫描寄存器的内容（即，错误的字线地址信息）与输入字线地址进行比较，并且如果找到匹配项，则取消选择主字线或字线，并选择冗余字线或字线。

公开(公告)号：US08850277B2

公开(公告)日：2014-09-30

申请号：US13183471

申请日：2011-07-15

申请人： Karen Amirkhanyan ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

发明人： Karen Amirkhanyan ,  Hayk Grigoryan ,  Gurgen Harutyunyan ,  Tatevik Melkumyan ,  Samvel Shoukourian ,  Alex Shubat ,  Valery Vardanian ,  Yervant Zorian

IPC分类号： G11C29/00 ,  G11C29/08 ,  G11C29/10 ,  G11C11/41

CPC分类号： G11C29/08 ,  G11C11/41 ,  G11C29/10

摘要： A method and system for testing an electronic memory. The method includes subjecting the electronic memory to a first test condition of a predetermined set of test conditions. The method also includes testing functionality of the electronic memory, a first plurality of times, for the first test condition using a predetermined test algorithm. The method further includes checking availability of a second test condition from the predetermined set of test conditions if the functionality of the electronic memory is satisfactory. Further, the method includes testing the functionality of the electronic memory, a second plurality of times, for the second test condition using the predetermined test algorithm if the second test condition is available. Moreover, the method includes accepting the electronic memory for use in a product if the functionality of the electronic memory is satisfactory.

摘要翻译： 一种用于测试电子存储器的方法和系统。 该方法包括使电子存储器经受预定的一组测试条件的第一测试条件。 该方法还包括使用预定的测试算法对于第一测试条件首次多次测试电子存储器的功能。 该方法还包括如果电子存储器的功能是令人满意的，则从预定的测试条件组检查第二测试条件的可用性。 此外，该方法包括如果第二测试条件可用，则使用预定测试算法来测试第二测试条件的电子存储器的功能，第二多次。 此外，如果电子存储器的功能令人满意，则该方法包括接受用于产品的电子存储器。

公开(公告)号：US07458005B1

公开(公告)日：2008-11-25

申请号：US11524691

申请日：2006-09-21

申请人： Alex Shubat

发明人： Alex Shubat

IPC分类号： G11C29/22 ,  G11C29/40

CPC分类号： G11C29/026 ,  G11C16/04 ,  G11C29/02 ,  G11C29/028 ,  G11C29/24 ,  G11C29/50 ,  G11C29/50004

摘要： A system and method for effectuating a self-timed clock (STC) loop for memory access operations. In one embodiment, the method includes configuring a particular access margin value setting based on configuration data of at least one memory instance of a memory device; and applying the particular access margin value setting to a reference cell assembly associated with the at least one memory instance for facilitating generation of a self-timed clock signal that is optimized for the at least one memory instance.

摘要翻译： 用于实现用于存储器访问操作的自定时钟（STC）循环的系统和方法。 在一个实施例中，该方法包括基于存储器件的至少一个存储器实例的配置数据来配置特定访问边缘值设置; 以及将所述特定访问边缘值设置应用于与所述至少一个存储器实例相关联的参考单元组件，以便于为所述至少一个存储器实例优化的自定时钟信号的产生。

公开(公告)号：US07406620B2

公开(公告)日：2008-07-29

申请号：US11503641

申请日：2006-08-14

申请人： Alex Shubat ,  Randall Lee Reichenbach

发明人： Alex Shubat ,  Randall Lee Reichenbach

IPC分类号： G06F11/00

CPC分类号： G11C29/4401 ,  G11C29/16 ,  G11C29/48 ,  G11C29/785 ,  G11C29/802 ,  G11C2029/0401

摘要： In one embodiment, a computer-implemented system for compiling a fuse assembly for a memory is disclosed. The claimed embodiment comprises: means for defining a memory group including at least one memory instance, each memory instance being characterized by its memory configuration data; means for determining number of fuses required for each memory instance based on its configuration data; means for automatically passing fuse information relating to the number of fuses to a fuse compiler; and means for generating, based on the fuse information, a fuse box assembly having a plurality of fuses organized into a set of fuse segments, each segment corresponding to a particular memory instance of the memory group.

摘要翻译： 在一个实施例中，公开了一种用于编译用于存储器的熔丝组件的计算机实现的系统。 所要求保护的实施例包括：用于定义包括至少一个存储器实例的存储器组的装置，每个存储器实例由其存储器配置数据表征; 用于根据其配置数据确定每个存储器实例所需的保险丝数量的装置; 用于自动将与保险丝数量相关的熔丝信息传送到保险丝编译器的装置; 以及用于基于所述保险丝信息产生具有组织成一组熔丝段的多个熔丝的熔丝盒组件的装置，每个段对应于所述存储器组的特定存储器实例。

公开(公告)号：US06556490B2

公开(公告)日：2003-04-29

申请号：US10099750

申请日：2002-03-15

申请人： Alex Shubat ,  Chang Hee Hong

发明人： Alex Shubat ,  Chang Hee Hong

IPC分类号： G11C700

CPC分类号： G11C29/848 ,  G11C29/785 ,  G11C29/802

摘要： A system and method for redundancy implementation in an integrated semiconductor device having at least one memory instance that includes a prime memory array and a redundant portion. A fuse box register is provided outside the memory macro cell associated with the memory instance. The fuse box register is operable to store location information pertaining to a faulty portion in the prime memory array. A redundancy scan storage element in the memory instance is operable to receive the location information from the fuse box register, which location information is used for replacing at least a part of the faulty portion in the prime memory array with at least a part of the redundant portion.

公开(公告)号：US5568085A

公开(公告)日：1996-10-22

申请号：US242947

申请日：1994-05-16

申请人： Boaz Eitan ,  Reza Kazerounian ,  Alex Shubat ,  John H. Pasternak

发明人： Boaz Eitan ,  Reza Kazerounian ,  Alex Shubat ,  John H. Pasternak

IPC分类号： G05F3/24 ,  G05F1/10

CPC分类号： G05F3/242

摘要： A unit for stabilizing the voltage on a capacitive node of a memory array, such as a common node bit line (CNBL), is disclosed. The unit includes an amplifier connected to the CNBL line and to one voltage source and a leaker connected to the CNBL line and to the other voltage supply, where the two voltage supplies can be the positive and ground supplies. The leaker is much smaller then the amplifier thereby to remove current from the CNBL line when there is little or no activity in The memory array. An alternative version of the unit which is also operative for standby operation is disclosed. In this embodiment, there is a switchable high power unit activatable during an active mode and a low power unit. Both units include an amplifier and a leaker connected as in the previous embodiment. The leakers are much smaller then the amplifiers and the amplifier of the high power unit is much larger than the amplifier of the low power unit. The high power unit also includes control transistors for disabling its amplifier and leaker during the standby mode.

摘要翻译： 公开了一种用于稳定诸如公共节点位线（CNBL）的存储器阵列的电容性节点上的电压的单元。 该单元包括连接到CNBL线的放大器和连接到CNBL线和另一个电压源的一个电压源和漏斗，其中两个电压源可以是正和地电源。 漏电器比放大器小得多，从而当存储器阵列中存在很少或没有活动时，从CNBL线路中去除电流。 公开了一种也可用于备用操作的单元的替代版本。 在该实施例中，存在可激活的高功率单元，其可在活动模式和低功率单元期间激活。 两个单元包括如前述实施例中那样连接的放大器和漏斗。 泄漏器比放大器小得多，大功率单元的放大器比低功率单元的放大器大得多。 高功率单元还包括用于在待机模式期间禁用其放大器和漏斗的控制晶体管。

公开(公告)号：US07093156B1

公开(公告)日：2006-08-15

申请号：US10144020

申请日：2002-05-13

申请人： Alex Shubat ,  Randall Lee Reichenbach

发明人： Alex Shubat ,  Randall Lee Reichenbach

IPC分类号： G06F11/00

CPC分类号： G11C29/4401 ,  G11C29/16 ,  G11C29/48 ,  G11C29/785 ,  G11C29/802 ,  G11C2029/0401

摘要： An embedded test and repair (ETR) scheme and interface for generating a self-test-and-repair (STAR) memory device using an integrated design environment. User interface and supporting program code is operable to provide a dialog box for defining a memory group that includes one or more memory instances, each having corresponding fuse element requirements based on its configuration data. BIST elements and a processor compiler for providing ETR functionality are also specified via suitable portions of the integrated GUI. A fuse equation is employed for computing the number of fuses for each memory instance, which equation is derived based on the memory configuration. Fuse information for each memory instance is automatically passed to a fuse compiler that generates a fuse box having an appropriate number of fuses that can accommodate the fuse requirements of the memory instances of the group.

摘要翻译： 嵌入式测试和修复（ETR）方案和接口，用于使用集成设计环境生成自检和维修（STAR）存储器设备。 用户界面和支持程序代码可操作以提供用于定义包括一个或多个存储器实例的存储器组的对话框，每个存储器实例基于其配置数据具有对应的熔丝元件要求。 BIST元件和用于提供ETR功能的处理器编译器也通过集成GUI的适当部分来指定。 采用熔丝方程来计算每个存储器实例的保险丝数量，该方程式基于存储器配置导出。 每个存储器实例的保险丝信息被自动传递到保险丝编译器，该保险丝编译器产生具有适当数量的保险丝的保险丝盒，该保险丝盒可以适应该组的存储器实例的保险丝要求。

公开(公告)号：US5432730A

公开(公告)日：1995-07-11

申请号：US170130

申请日：1993-12-20

申请人： Alex Shubat ,  Boaz Eitan

发明人： Alex Shubat ,  Boaz Eitan

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/78

CPC分类号： H01L27/115 ,  G11C16/0491

摘要： There is provided an EPROM array including columns of EPROM cells, three types of diffusion bit lines, two types of metal lines and two types of select transistors. The metal lines are formed of metal 1 lines and metal 2 lines, where the metal 1 lines are formed into segmented lines and continuous lines and the metal 2 lines are continuous. The diffusion bit lines are formed of short, medium and continuous lines, where the medium length diffusion lines are associated with one segmented metal 1 line and one metal 2 line, the continuous lines are associated with one continuous metal 1 line and the short bit lines are formed of short segments and are not associated with metal lines. The diffusion lines repeat in the following order: medium length, short, continuous, short. One type of select transistor connects one short diffusion line to one metal 1 line and the second type of select transistor connects one segmented metal 1 line to one metal 2 line. Each column of EPROM cells are located between two neighboring diffusion lines.

摘要翻译： 提供了包括EPROM单元列，三种扩散位线，两种类型的金属线和两种类型的选择晶体管的EPROM阵列。 金属线由金属线1和金属2线形成，其中金属1线形成分段线和连续线，并且金属2线是连续的。 扩散位线由短，中等和连续的线形成，其中中长度扩散线与一个分段的金属1线和一个金属2线相关联，连续线与一条连续金属1线和短位线 由短段形成并且不与金属线相关联。 扩散线按以下顺序重复：中长度，短，连续，短。 一种选择晶体管将一个短扩散线连接到一个金属1线，而第二种类型的选择晶体管将一个分段的金属1线连接到一个金属2线。 每列EPROM单元位于两个相邻的扩散线之间。