公开(公告)号：US20080070403A1

公开(公告)日：2008-03-20

申请号：US11985686

申请日：2007-11-16

Applicant: Klaus Goller ,  Alexander Reb ,  Grit Schwalbe

Inventor： Klaus Goller ,  Alexander Reb ,  Grit Schwalbe

IPC: H01L21/4763

CPC classification number: H01L23/485 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses. This is to achieve that the second terminal is contacted in the production of the second contact terminal.

Abstract translation: 在接触端子的方法中，提供了具有第一端子和第二端子的基板，第一端子的端子表面位于比第二端子的表面离基板表面更短的距离处。 在基板表面上形成有第一绝缘层，其中形成用于暴露第一端子的端子表面的接触通孔。 接触通孔填充有导电材料，并且在第一绝缘层上形成第二绝缘层，并在接触孔上填充有导电材料。 使用蚀刻掩模，通过第二和第一绝缘层蚀刻用于暴露填充接触通孔的导电材料的第一凹部和第二凹槽，用于暴露第二端子表面。 用于产生第一和第二接触端子的导电材料被引入到第一和第二凹槽中。 这是为了实现在第二接触端子的制造中第二端子接触。

公开(公告)号：US07666783B2

公开(公告)日：2010-02-23

申请号：US11985686

申请日：2007-11-16

Applicant: Klaus Goller ,  Alexander Reb ,  Grit Schwalbe

Inventor： Klaus Goller ,  Alexander Reb ,  Grit Schwalbe

IPC: H01L21/4763

CPC classification number: H01L23/485 ,  H01L21/76802 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: In a method of contacting terminals, a substrate having a first terminal and a second terminal is provided, a terminal surface of the first terminal being located at a shorter distance from a substrate surface than a surface of the second terminal. A first insulating layer, in which a contact via is formed for exposing the terminal surface of the first terminal, is formed on the substrate surface. The contact via is filled with a conductive material, and a second insulating layer is formed on the first insulating layer and on the contact via filled with the conductive material. Using an etching mask, a first recess for exposing the conductive material filling the contact via, and a second recess are etched through the second and first insulating layers for exposing the second terminal surface. A conductive material for producing first and second contact terminals is introduced into the first and second recesses. This is to achieve that the second terminal is contacted in the production of the second contact terminal.

Abstract translation: 在接触端子的方法中，提供了具有第一端子和第二端子的基板，第一端子的端子表面位于比第二端子的表面离基板表面更短的距离处。 在基板表面上形成有第一绝缘层，其中形成用于暴露第一端子的端子表面的接触通孔。 接触通孔填充有导电材料，并且在第一绝缘层上形成第二绝缘层，并在接触孔上填充有导电材料。 使用蚀刻掩模，通过第二和第一绝缘层蚀刻用于暴露填充接触通孔的导电材料的第一凹部和第二凹槽，用于暴露第二端子表面。 用于产生第一和第二接触端子的导电材料被引入到第一和第二凹槽中。 这是为了实现在第二接触端子的制造中第二端子接触。

公开(公告)号：US07141507B2

公开(公告)日：2006-11-28

申请号：US11065342

申请日：2005-02-25

Applicant: Oliver Genz ,  Markus Kirchhoff ,  Stephan Machill ,  Alexander Reb ,  Barbara Schmidt ,  Momtchil Stavrev ,  Maik Stegemann ,  Stephan Wege

Inventor： Oliver Genz ,  Markus Kirchhoff ,  Stephan Machill ,  Alexander Reb ,  Barbara Schmidt ,  Momtchil Stavrev ,  Maik Stegemann ,  Stephan Wege

IPC: H01L21/302

CPC classification number: H01L21/76811 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144

Abstract: A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Abstract translation: 一种制造半导体结构的方法，包括制备半导体衬底，并在所述半导体衬底的表面上产生下部第一，中间第二和上部第三掩模层。 该方法还包括在上部第三掩蔽层中形成至少一个第一窗口，使用用于传送第一窗口的第一窗口构造中间第二掩蔽层，使用用于传送第一窗口的第一窗口构造下部第一掩蔽层，以及 扩大第一个窗口形成第二个窗口。 该方法还包括：使用第二窗口重建中间第二掩蔽层，使用结构化的下部第三掩蔽层，使用第二窗口重构下部第一掩蔽层，并重构半导体衬底，构建半导体衬底; 使用重组的下三层掩蔽层。

公开(公告)号：US07018781B2

公开(公告)日：2006-03-28

申请号：US10811509

申请日：2004-03-29

Applicant: Hans-Georg Fröhlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

Inventor： Hans-Georg Fröhlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

IPC: G03F7/00

CPC classification number: H01L27/10888 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76897 ,  H01L27/10894

Abstract: Disclosed is a method for fabricating a contract hole plane in a memory module with an arrangement of memory cells each having a selection transistor. The methods can be utilized during the production of dynamic random access memory (DRAM) modules.

Abstract translation: 公开了一种在具有选择晶体管的存储单元的布置的存储器模块中制造合同孔平面的方法。 可以在生产动态随机存取存储器（DRAM）模块期间利用这些方法。

公开(公告)号：US20050196952A1

公开(公告)日：2005-09-08

申请号：US11065342

申请日：2005-02-25

Applicant: Oliver Genz ,  Markus Kirchhoff ,  Stefan Machill ,  Alexander Reb ,  Barbara Schmidt ,  Momtchil Stavrev ,  Maik Stegeman ,  Stephan Wege

Inventor： Oliver Genz ,  Markus Kirchhoff ,  Stefan Machill ,  Alexander Reb ,  Barbara Schmidt ,  Momtchil Stavrev ,  Maik Stegeman ,  Stephan Wege

IPC: H01L21/027 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8244

CPC classification number: H01L21/76811 ,  H01L21/0276 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144

Abstract: A method for producing a semiconductor structure including preparing a semiconductor substrate, and generating a lower first, a middle second and an upper third masking layer on a surface of the semiconductor substrate. The method further includes forming at least one first window in the upper third masking layer, structuring the middle second masking layer using the first window for transferring the first window, structuring the lower first masking layer using the first window for transferring the first window, and enlarging the first window to form a second window. The method for further includes restructuring the middle second masking layer using the second window for transferring the second window, structuring the semiconductor substrate, using the structured lower third masking layer, restructuring the lower first masking layer using the second window, and restructuring the semiconductor substrate using the restructured lower third masking layer.

Abstract translation: 一种制造半导体结构的方法，包括制备半导体衬底，并在所述半导体衬底的表面上产生下部第一，中间第二和上部第三掩模层。 该方法还包括在上部第三掩蔽层中形成至少一个第一窗口，使用用于传送第一窗口的第一窗口构造中间第二掩蔽层，使用用于传送第一窗口的第一窗口构造下部第一掩蔽层，以及 扩大第一个窗口形成第二个窗口。 该方法还包括：使用第二窗口重建中间第二掩蔽层，使用结构化的下部第三掩蔽层，使用第二窗口重构下部第一掩蔽层，并重构半导体衬底，构建半导体衬底; 使用重组的下三层掩蔽层。

公开(公告)号：US20050090114A1

公开(公告)日：2005-04-28

申请号：US10493148

申请日：2002-10-29

Applicant: Michael Rogalli ,  Alexander Reb ,  Lars Volkel ,  Maik Stegemann

Inventor： Michael Rogalli ,  Alexander Reb ,  Lars Volkel ,  Maik Stegemann

IPC: G03F7/40 ,  H01L21/3213 ,  H01L21/302 ,  H01L21/461

CPC classification number: H01L21/32136 ,  G03F7/40 ,  G03F7/405 ,  H01L21/32135

Abstract: The invention relates to a process for the production of a semiconductor apparatus, in which an etch step is carried out after an exposure step using light having a wavelength of 193 nm and a development step, the etch gas used containing an added reactive monomer. As a result, polymerization of the surface and hence sidewall passivation of the photoresist used are achieved.

Abstract translation: 本发明涉及一种制造半导体装置的方法，其中在使用波长为193nm的光和显影步骤的曝光步骤之后进行蚀刻步骤，所用的蚀刻气体含有添加的反应性单体。 结果，实现了表面的聚合，并因此实现了光致抗蚀剂的侧壁钝化。

公开(公告)号：US20050003308A1

公开(公告)日：2005-01-06

申请号：US10811509

申请日：2004-03-29

Applicant: Hans-Georg Frohlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

Inventor： Hans-Georg Frohlich ,  Oliver Genz ,  Werner Graf ,  Stefan Gruss ,  Matthias Handke ,  Percy Heger ,  Lars Heineck ,  Antje Laessig ,  Alexander Reb ,  Kristin Schupke ,  Momtchil Stavrev ,  Mirko Vogt

IPC: H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  G03F7/00

CPC classification number: H01L27/10888 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76837 ,  H01L21/76897 ,  H01L27/10894

Abstract: In order to fabricate a contact hole plane in a memory module with an arrangement of memory cells each having a selection transistor, on a semiconductor substrate with an arrangement of mutually adjacent gate electrode tracks on the semiconductor surface, an insulator layer is formed on the semiconductor surface and a sacrificial layer is subsequently formed on the insulator layer, then material plugs are produced on the sacrificial layer for the purpose of defining contact openings between the mutually adjacent gate electrode tracks, the sacrificial layer is etched to form material plugs with the underlying sacrificial layer blocks, after the production of the vitreous layer with uncovering of the sacrificial layer blocks above the contact openings between the mutually adjacent gate electrode tracks, an essentially planar surface being formed, then the sacrificial layer material is etched out from the vitreous layer and the uncovered insulator material is removed above the contact openings on the semiconductor surface and, finally, the contact opening regions are filled with a conductive material.

Abstract translation: 为了在具有选择晶体管的存储单元的布置的存储器模块中制造接触孔平面，在半导体衬底上具有半导体表面上相互邻近的栅极电极轨迹的布置，在半导体上形成绝缘体层 表面和牺牲层随后形成在绝缘体层上，然后在牺牲层上产生材料插塞以便限定相互相邻的栅极电极轨道之间的接触开口，牺牲层被蚀刻以形成具有下面牺牲的材料塞 在玻璃质层的生产之后，在相邻的栅电极轨道之间的接触开口上方露出牺牲层块，形成基本平坦的表面，然后从玻璃质层蚀刻牺牲层材料，并且 未覆盖的绝缘体材料在触点上方移除 并且最后，用导电材料填充接触开口区域。