摘要:
A method of controlling surface non-uniformity of a wafer in a polishing operation includes (a) providing a model for a wafer polishing that defines a plurality of regions on a wafer and identifies a wafer material removal rate in a polishing step of a polishing process for each of the regions, wherein the polishing process comprises a plurality of polishing steps, (b) polishing a wafer using a first polishing recipe based upon an incoming wafer thickness profile, (c) determining a wafer thickness profile for the post-polished wafer of step (b), and (d) calculating an updated polishing recipe based upon the wafer thickness profile of step (c) and the model of step (a) to maintain a target wafer thickness profile. The model can information about the tool state to improve the model quality. The method can be used to provide feedback to a plurality of platen stations.
摘要:
A method and apparatus for diagnosing faults. Process data is analyzed using a first metric to identify a fault. The process data was obtained from a manufacturing machine running a first recipe. A fault signature that matches the fault is identified. The identified fault signature was generated using a second metric and/or a second recipe. At least one fault class that is associated with the fault signature is identified.
摘要:
Methods and apparatuses for presenting multivariate fault contributions in a user interface are described. A user interface is provided to illustrate a fault for a sample manufactured by a process containing multiple variables, each having at least two components. The user interface presents one group of components of the multiple variables in a first axis and a second group of components of the multiple variables in a second axis and graphically illustrates contributions to the fault associated with the multiple variables by associating a contribution of each component in the one group of components of the multiple variables to each corresponding component in the second group of components of the multiple variables.
摘要:
A method for monitoring performance of an advanced process control system for at least one process output includes calculating a variance of a prediction error for a processing performance and/or a probability for violating specification limits of the processing performance of the at least one process output. If the variance of the prediction error is calculated, the method also includes calculating a model health index. If the probability for violating specification limits is calculated, the method further includes calculating a process health index.
摘要:
Semiconductor wafers are processed in conjunction with a manufacturing execution system using a run-to-run controller and a fault detection system. A recipe is received from the manufacturing execution system by the run-to-run controller for controlling a tool. The recipe includes a setpoint for obtaining one or more target wafer properties. Processing of the wafers is monitored by measuring processing attributes including fault conditions and wafer properties using the fault detection system and one or more sensors. Setpoints of the recipe may be modified at the run-to-run controller according to the processing attributes to maintain the target wafer properties, except in cases when a fault condition is detected by the fault detection system. Thus, data acquired in the presence of tool or wafer fault conditions are not used for feedback purposes. In addition, fault detection models may be used to define a range of conditions indicative of a fault condition. In these cases, the fault detection models may be modified to incorporate, as parameters, setpoints of a recipe modified by a run-to-run controller.
摘要:
Semiconductor wafers are processed in a fab in a manner that integrates control at multiple functional unit levels. Examples of functional units include fabs, modules, tools, and the like. Initially, a number of functional unit property targets are received at a functional unit. The functional unit property targets are utilized to generate a number of tool targets for any number of tool level functional units. From there, the tool targets are forwarded to the corresponding tool level functional units. At these tool level functional units, a number of tool recipes, each of which define a number of process setpoints, may be generated by processing the tool targets. The process setpoints define a number of parameters which must be satisfied in order to attain the corresponding tool targets. In addition, in at least some embodiments, the tool targets and tool recipes are determined utilizing feedback information including functional unit states and measurements of controlled parameters.
摘要:
In one embodiment, an inline defect analysis method includes receiving geometric characteristics of individual defects and design data corresponding to the individual defects, determining which of the individual defects are likely to be nuisance defects using the geometric characteristics and the corresponding design data, and refraining from sampling the defects that are likely to be nuisance defects.
摘要:
A method of controlling surface non-uniformity of a wafer in a polishing operation includes (a) providing a model for a wafer polishing that defines a plurality of regions on a wafer and identifies a wafer material removal rate in a polishing step of a polishing process for each of the regions, wherein the polishing process comprises a plurality of polishing steps, (b) polishing a wafer using a first polishing recipe based upon an incoming wafer thickness profile, (c) determining a wafer thickness profile for the post-polished wafer of step (b), and (d) calculating an updated polishing recipe based upon the wafer thickness profile of step (c) and the model of step (a) to maintain a target wafer thickness profile. The model can information about the tool state to improve the model quality. The method can be used to provide feedback to a plurality of platen stations.
摘要:
In one embodiment, a method for predicting yield includes calculating a criticality factor (CF) for each of a plurality of defects detected in an inspection process step of a wafer, and determining a yield-loss contribution of the inspection process step to the final yield based on CFs of the plurality of defects and the yield model built for a relevant design. The yield-loss contribution of the inspection process step is then used to predict the final yield for the wafer.
摘要:
Embodiments of the present invention provide methods and apparatuses for determining factors for design consideration in yield analysis of semiconductor fabrication. In one embodiment, a computer-implemented method for determining factors for design consideration in yield analysis of semiconductor fabrication includes obtaining a geometric characteristic of a defect on a chip and obtaining design data of the chip, where the design data is associated with the defect. The method further includes determining a criticality factor of the defect based on the geometric characteristic and the design data, and outputting the criticality factor.